Testing 3D stacked ICs

Imec Belgium and Cadence Design Systems have announced technology that delivers an automated test solution for design teams deploying 3D stacked ICs (3D-ICs).

This addresses the test challenges involved as electronics companies increasingly turn to 3D-ICs as a way to increase circuit density and achieve better performance at lower power dissipation for mobile and other applications where space is at a premium.

The collaboration provides the design-for-test and automatic test pattern generation technology that will make it easier to test 3D-ICs with ‘through-silicon via’ functionality and help ensure that the stacked system will work as intended.

Insights gained during its research program on TSV-based 3D-IC design and technology enabled imec to extend the DFT architecture for conventional 2D-ICs with several novel features.

The new architecture is based on the concept of die-level test wrappers, which enable testing chips with TSVs and micro-bumps both before (‘pre-bond test’), during (‘mid-bond test’) and after (‘post-bond test’) stacking, as well as after packaging.