Japanese companies add support for SystemVerilog

The Verification Methodology Manual (VMM) for SystemVerilog has been endorsed by the Semiconductor Technology Academic Research Centre (STARC) and major electronics companies in Japan as a reference to develop advanced verification environments based on the IEEE standard SystemVerilog language.

The Japanese-language edition of the manual will be published by CQ Publishing in Japan. More than 1800 copies of the English-language edition have been sold to date.

The manual, co-authored by verification experts from ARM and Synopsys, describes how to use SystemVerilog to create comprehensive verification environments using coverage-driven, constrained-random and assertion-based techniques, and specifies library building blocks for interoperable verification components.

The VMM for SystemVerilog, reviewed by verification engineers from more than 30 semiconductor industry companies, helps enable chip development teams to achieve measurable functional coverage goals in less time with less effort, giving verification engineers and managers the confidence to tape out complex system-on-chip (SoC) and silicon intellectual property (IP) designs.

"The VMM for SystemVerilog is our recommended reference book to architect SystemVerilog verification environments", said Yoshiharu Furui, senior manager, IP Reuse Engineering Group at STARC Japan.

"It defines the state-of-the-art for advanced, coverage-driven functional verification that engineers can use to increase chip development productivity and quality, and will complement the IP Functional Verification Guide being developed by the STARC IP Reuse Engineering Group."