IMEC shifts research program

IMEC, an independent nanoelectronics and nanotechnology research institute, has extended its 193 nm immersion lithography research program and double-patterning techniques to meet the stringent scaling roadmaps, especially of Flash. The program now runs hyper-NA immersion, double-patterning immersion and EUV in parallel.

The company states extreme UV will be needed to accommodate the pitch requirements for sub-32 nm CMOS, but it still has a long way to go before it can be inserted into manufacturing. As such, 193nm immersion lithography needs to be extended down to 32nm CMOS. To meet the roadmaps, especially of Flash, extensive use of double-patterning techniques may also be required.

IMEC now runs research programs on hyper-NA immersion, double-patterning immersion and EUV in parallel to deal with the challenges for the (sub)-32 nm node.

Within the hyper-NA research program, IMEC focuses on alternative mask stacks, high-index liquids and resists, XT:1700i lens and illumination characterisation and immersion baseline including resist, defectivity and scanner.

The company will use results achieved over the past year in its 193 nm immersion program: reduction of patterned defectivity, improvement of CD uniformity and overlay performance.

The company's double patterning research will be linked with its device programs on CMOS for logic and also in its advanced-memory program. Double-patterning research topics include layout-split methodology and exploration of alternative patterning steps to improve double-patterning cost of ownership.

Existing research in the Flash program includes: the study of new cell concepts (nitride concept); implementation of high-k materials; reliability and characterisation.

Several logic and Flash cells will be used as demonstrators in the program on (sub)-32 nm lithography.

Research within the EUV program includes resists and reticle development and assessment of the EUV alpha demo tool.