The story of PCI Express

As PC technology has evolved, the ability to use standard desktop and portable computers for test, control and design applications has improved dramatically.

Economies of scale have made it much more cost effective to use the GHz processing and gigabytes of memory on standard computers than for vendors to install processors and memory in measurement instruments.

At the same time, commercially available silicon technologies designed for modern electronics have been repurposed by the test and control industries.

For example, analog and digital converters originally designed for electronic devices like mobile phones and DVD players now also provide incredible speed and accuracy for PC-based data acquisition devices.

These high production commercial components are available at fractions of the cost and in much faster design cycles than it would take for instrumentation vendors to design their own components.

By using these advances in PC and silicon technologies, low-cost PC-based plug-in devices can now perform measurements and control with accuracy and processing speed never before available with traditional instruments.

As acquisition rates increase, a common bottleneck for these virtual instruments has been the ability to quickly and easily transfer data from the measurement device into PC memory.

Traditional bus technologies such as the general-purpose interface bus (GPIB) and serial RS232 often require instrumentation vendors to install local memory on the instrument itself to temporarily store data that cannot be transferred to the PC fast enough because of bus bandwidth limitations.

As the PC industry has standardised on the PCI bus over the past decade, plug-in devices designed for this bus have realised a 10-times increase in data bandwidth versus GPIB and in many cases the requirement for deep onboard memory has been reduced.

At the same time, cabled bus technologies such as USB have become extremely popular for test and measurement applications because of their portability and dummy-proof usability.

As virtual instruments acquire more data at faster rates by using the latest analog and digital converter technologies, systems using PCI and USB have again encountered the bus itself as the limiting factor in efficiently transferring data to PC memory.

To address this increasing hunger for bandwidth, new technologies including PCI Express and high-speed USB 2.0 are now making it possible to stream huge amounts of data from devices to the PC while ensuring backward compatibility and improving ease of use.

PCI Express was jointly developed by PC and peripheral vendors including Intel and became available in standard desktop PCs in 2004.

Already, most desktop machines from the leading suppliers include at least one PCI Express slot. PCI Express maintains software compatibility with traditional PCI, but replaces the physical bus with a high-speed (2.5 Gbps) serial bus.

Data is sent in packets through pairs of transmit and receive signals called lanes, which enable 250 MBps bandwidth per direction, per lane.

Multiple lanes can be grouped together into x1 ('by-one'), x2, x4, x8, x12, x16 and x32 lane widths to increase bandwidth to the slot. And unlike PCI, which divides bandwidth between all devices on the bus, PCI Express provides dedicated bandwidth to each slot in the system.

Applications such as data acquisition and waveform generation require guaranteed bandwidth and deterministic latency. Sufficient bandwidth is required to ensure that data can be transferred to memory fast enough without being lost or overwritten.

Latency is the time it takes for a signal such as a configuration or start command to be sent and received. Long latency is characteristic of buses such as ethernet and is a primary reason this bus has not been widely adopted for PC-based test.

The original PCI specification did not address these issues because high-speed data streaming applications on the PC were not prevalent at the time it was introduced. As a result, data acquisition devices that adopted the bus required onboard memory for data buffering to handle the varying bandwidths available during data transfers.

Today, isochronous data transfers such as uncompressed streaming audio and video require the I/O subsystem of the PC to provide guaranteed bandwidth and deterministic latency to prevent data glitches.

To address these needs, PCI Express incorporates an isochronous data transfer mode, allowing a device to reserve a defined amount of bandwidth with deterministic latency.

Data acquisition applications also benefit from this feature because PCI Express devices require less memory than traditional PCI for data buffering purposes.

PCI Express improves data bandwidth. The initial signalling frequency provided by the specification of 2.5 Gbps provides up to 60 times (with a x16 slot) the usable bandwidth of 32 bit, 33 MHz PCI and this signalling frequency is expected to increase with advances in silicon technology to 10 Gbps/direction - the practical limit for signals in copper.

Because of the lane topology of PCI Express, data acquisition vendors can implement a PCI Express connector with the number of lanes suitable to the requirements of the device.

Devices with smaller connectors can be 'up-plugged' into larger host connectors on the motherboard, improving hardware compatibility and flexibility.

Software compatibility is also ensured by the PCI Express specification. The configuration space and programmability of PCI Express devices are unchanged from the traditional PCI methodology. In fact, all operating systems are able to boot without modification on a PCI Express architecture.

At boot time, the operating system can discover all the PCI Express devices present and then allocate system resources such as memory, I/O space and interrupts to create an optimal system environment.

And because the PCI Express physical layer is transparent to application software, programs originally written for PCI devices can run unchanged on PCI Express devices that have the same functionality.

This backward compatibility of PCI Express software with traditional PCI is critical in preserving the software investments of both vendors and users.

Similar to the improvements PCI Express offers plug-in devices, USB 2.0 high speed has introduced improvements in bandwidth and signal latency for externally cabled data acquisition devices.

USB has become the de-facto standard for cabling peripheral devices to the PC and data acquisition devices are no exception. The plug-and-play and hot-pluggable features of the bus make it extremely easy to use, enabling a connected device to be automatically detected and configured by the host PC.

Drivers are dynamically loadable and unloadable, with no need to power down the device or PC during installation.

Another unique benefit to USB 2.0 is that the bus provides power on the same cable that carries the data signal, often simplifying connectivity and portability by eliminating dedicated AC power cables.

The USB 2.0 specification made significant improvements in both bandwidth and latency versus USB 1.1 The 1.5 MBps rate provided by USB 1.1 quickly became a limiting factor for large data size transfers such as high-speed data acquisition.

USB 2.0 improved that rate by 40 times, enabling bandwidths up to 60 MBps. Like PCI Express, USB 2.0 provides isochronous transfers, but also adds another three data transfer modes that can be enabled by the manufacturer.

For example, the bulk transfer mode provides data receive confirmations to ensure error-free transfer for applications such as data acquisition in which data integrity is paramount.

The release of the USB 2.0 standard created a total of three classes of USB devices: low-speed (1.5 Mbps), full-speed (12 Mbps), and high-speed (480 Mbps) devices. USB 2.0 is both forward and backward compatible with USB 1.1 and low-speed, full-speed and high-speed devices can all coexist on a single USB port.

In addition to bandwidth improvements, USB 2.0 also introduced new ways to improve the efficiency of data transfers.

Data frames - the time segments allotted for packet transfers - were cut from 1 ms into eight 125 µs frames and the number of data bytes transferred per frame was significantly increased.

Because large data packets can consume large amounts of bandwidth, new handshaking commands were introduced to ensure that the host is ready and capable of receiving the entire queued data packet.

USB 2.0 also introduced split transactions which prevent full-speed and low-speed devices from slowing the bus down. With split transactions, the host can communicate with high-speed devices on the bus without waiting for slower devices to return communication.

As PC bus technologies like PCI Express and USB 2.0 continue to improve data bandwidth, performance and ease of use, the benefits of using PC-based devices for measurements and control are even more dramatic.

In fact, by virtue of being based on computer technology, virtual instruments will always improve as new communication, processing and memory technologies become available. As PCI Express and USB 2.0 continue in their adoption cycles, there will be several years of hybrid systems that use these new technologies in addition to traditional PCI and USB 1.1 buses and devices.

These transitions will be abridged by the software compatibilities of the new technologies with their predecessors as well as the physical compatibility between USB 1.1 and USB 2.0.

But the benefits of these two new technologies are clear and as PC-based test and control systems continue to push bandwidth requirements, PCI Express and USB 2.0 will enable faster data transfers to PCs where the ever increasing processor speeds and memory depths can be full used.

USB 2.0 has spurred a whirlwind of new easy-to-use data acquisition devices, and with the release of PCI Express, the next generation of plug-in data acquisition devices adopting the new bus standard is sure to follow.