Mixed-signal 'scopes speed FPGA debug

Digital designers have long reached for an oscilloscope as the tool of first choice for debug. As FPGAs have become the centrepiece of digital design, the need to quickly debug systems that include programmable logic is stronger than ever.

However, traditional oscilloscope technology has not kept up with functional debugs of FPGAs. A new breed of oscilloscopes, known as mixed signal oscilloscopes, or MSOs for short, delivers needed capabilities to teams developing systems with FPGAs.

Like traditional oscilloscope measurements, MSOs offer the same feature set for taking parametric measurements to measure signal integrity, jitter and signal characterisation. Design teams can choose between versions that have either two or four analog input channels.

MSOs come in a variety of bandwidths ranging from 300 MHz to 1 GHz. These capabilities are important for checking signal parametrics.

For example, a designer can readily change I/O standards and drive strengths using Xilinx FPGA Editor and measure the real-world I/O characteristics using an MSO's scope channels.

The major difference between MSOs in traditional DSOs is the addition of 16 digital asynchronous sampling channels on the MSO. Design teams can choose how fast these digital channels sample. The digital channels offer deep memory storage that is independent of the analog channel memory storage.

Design teams can employ the capabilities of the digital channels in a number of different ways that are particularly valuable for teams developing systems that incorporate FPGAs.

Traditional oscilloscopes provide digital triggering capabilities that allow them to trigger on patterns across the analog channels. So, with a four-channel oscilloscope a design team can trigger on a single pattern that is up to four signals wide.

Debug often requires looking at buses using a specific event as the trigger condition. Using an MSO's digital channels, design teams can trigger on a digital pattern up to 16 signals wide.

This can be a powerful capability when needing to look at a machine, an embedded microcontroller or a data bus. In addition, users can also trigger and capture measurements across all four analog channels, extending the trigger width up to 20 signals as shown in Figure 1.

Figure 1: In addition to scope channels, mixed signal oscilloscopes provide 16 digital channels. This gives users the ability to trigger and display up to 20 signals simultaneously. The width of the digital channels is particularly well suited to measuring signals internal to Xilinx FPGAs.

While the digital channels can be used to make strictly digital measurements, their capabilities are best employed for looking at problems that are both functional and parametric in nature.

For example, triggering on a digital bus and having this trigger condition arm the scope measurement.

A design team within Agilent experienced an infrequent software glitch on an embedded product under development. This anomaly manifested itself very infrequently, about once a week. The software team developed diagnostics that caused the problem to happen more frequently.

With this software, the team found that the problem occurred during read cycles on a PCI bus which was embedded in an FPGA.

The team routed PCI status signal out to pins and connected the MSO's digital channels to these signals. Engineers quickly set up the MSO digital trigger on a PCI read cycle. The team then set the MSO scope channels to acquire when the MSO digital channels recorded a PCI bus read cycle.

With the ability to trigger on a specific bus cycle, the team was able to resolve the problem. It found a clock with too slow a rise time impacted primarily read cycles. The team modified the design and downloaded a new configuration file into the FPGA.

The combination of reprogammable FPGAs and MSO measurements allowed the team to correct the problem.

To access internal signals, design teams typically use the route out approach to bring signals to pins that can be probed using an oscilloscope. Using traditional oscilloscopes, designers have access to either two or four signals at a time.

This narrow signal visibility can complicate debug as a number of problems requires simultaneous visibility across a higher number of signals.

To access new signals the design team must change the design, re-synthesise, and run a new place and route to make their signals accessible to the oscilloscope. This process can take hours.

With the digital channels of an MSO, a design team has visibility of up to 16 internal FPGA signals at a time. The power of the MSO's digital channels can be further extended when combined with on-chip technologies such as Xilinx ChipScope Pro and Agilent FPGA dynamic probe.

ChipScope Pro allows design teams to incorporate an Agilent debug core in their FPGA design. The debug core, known as ATC2 for short, provides an easy way to route signals to pins, enables a faster set-up of the MSO, and allows the user to quickly measure new groups of internal signals. This capability extends the reach of the 16 digital channels into the FPGA design.

A state machine drives the process of sending out packetised 16 bit data along with a transaction ID. Parallel data is serialised, sent on a serial channel, de-serialised and brought into a monitor. A second state machine at the monitor drives the process of receiving the packets and stripping off the data and transaction IDs so the packets can be pulled off to external memory.

This machine also generates acknowledge IDs that are fed back to the transmit side to communicate that data was received. The designer originally dedicated 16 pins for a debug port.

Using Xilinx ChipScope Pro Core Inserter, the designer can set parameters on an ATC2 core. A benefit of Core Inserter is that no modification needs to be made to the original HDL design as core insertion occurs post-synthesis and before place and route.

The design team specifies, using Core Inserter, which internal signals to group together as an active signal bank. Place and route uses the original user constraint file so no additional work is required from the designer.

Core Inserter also produces a small file that contains the specified signal names and groups. This file, known as a .cdc, is read by the FPGA dynamic probe application running on the MSO. When a user changes which signal group is presented to the MSO, the instrument automatically uses this signal naming file to correctly update signal names on the display.

Versus the route-out approach that can take hours to bring new signals to pins, an FPGA dynamic probe allows the designer to access a new group of internal signals in about a second.

For fast debug, the design team needed visibility into four sections of the design. This designer created a core with four signal banks to give access to 64 signals, 16 at a time, over the 16 pin debug port as shown in Figure 2. ATC2 cores have then parameters set to have up to 64 signal banks providing access to 1024 internal signals with the MSO's 16 digital channels.

Figure 2: ATC2 cores, inserted using Xilinx ChipScope Pro, allow design teams to quickly switch which signals are connected to pins for measurement. Each ATC2 core can be given parameters with as little as one signal bank or as many as 64.

ATC2 cores can be configured as either timing (asynchronous) or state (synchronous) cores. Both types of cores are supported with the MSO. Xilinx Core Inserter injects a core into a design post synthesis and before place and route.

If the designer specified a timing core, the place and route tools do not put any flops between the signal being probed and the output pin. The routing of the signal to pin for measurement is treated as a false path. This allows the place and route tools to ignore any speed constraints associated with routing a specific signal to a pin.

The timing core does include a JTAG controller, but the controller typically runs very slowly (less than 5 MHz) as it is only used for small information exchanges such as selecting a new signal bank.

Timing cores can be effective as they allow a user to look at signals across multiple clock domains or at anomalies that have a duration less than one clock cycle. The primary trade-off associated with timing cores is that skew will exist between signal paths.

Traditional oscilloscopes as well as MSOs provide asynchronous acquisition. Samples are stored using an adjustable clock reference internal to the scope. This can make it difficult to accurately capture and decipher synchronous events as the instrument captures invalid transitions between clock cycles.

A more effective way of capturing synchronous information on a single clock domain is to set the parameters on an ATC2 core as a state core. A state core will have minimal impact on design timing due to its pipelined architecture. A total of four flops are placed between the signal being probed and an output pad as shown in Figure 3.

Figure 3: A pipelined architecture uses four stages to route a signal to the debug port using FPGA dynamic probe. This automated approach gives place and route tool flexibility to meet timing requirements. The router can use timing solely within the ATC2 core to move across the chip.

The design tools place the first flop as close as possible to the signal being probed. The additional three stages of pipelining allow the signal three clock cycles before reaching the output pad.

The pipelined architecture of the ATC2 core allows the place and route tools to have a much greater probability of meeting the original timing goals of the design.

As the core is synchronous, the place and route tools eliminate skew between signal paths. The primary trade-off with a state core is that it works with a single time domain. Using the state core approach, design teams that need to measure across clock domains can do so by inserting multiple state cores.

The MSO can access multiple ATC2 cores, one at a time, in a single FPGA or distributed across multiple FPGAs on a single scan chain.

The MSO's digital channels provide exclusively asynchronous acquisition. For FPGA debug, there is a method for allowing the MSO to display synchronous measurements, even though the initial acquisition occurs asynchronously.

The ATC2 state core outputs a clock signal and signal states synchronous with the clock. MSOs' digital channels acquire this pre-formatted state information. Then the MSO post processes this measurement using a state display feature that allows the user to specify one signal as the clock.

The MSO filters out to all transitions between valid states. This gives the capability of making synchronous measurements internal to the FPGA.

The reprogrammable nature of FPGA technology makes rapid iterative real-world debug a great companion to simulation. As FPGAs become even more sophisticated the need for efficient internal visibility increases.

Mixed signal oscilloscopes provide unique measurement capabilities that align with the needs of teams designing systems that incorporate FPGAs. Applications that help engineers exploit the digital measurement capabilities of MSOs are a catalyst for shorter development cycles and higher quality designs.