Improving solar cells with the microelectronics toolbox

To make solar energy generation cost-effective, the PV industry has to reduce its manufacturing costs well below 1 euro/Wp. This holds for all PV technologies.

To reach that goal, the crystalline Si-based PV industry will have to increase the solar cell’s efficiency while at the same time reduce the quantity of high-purity Si that is used. But this requires developing advanced cell concepts that put more stringent requirements on process steps such as doping, cleaning and surface passivation.

Several processes in the technology toolbox of CMOS are attractive to meet these requirements.

These tools can be adopted to decrease the solar cells euro/Wp, but they will have to be ‘solarised’, adapting them to the needs and requirements of the PV industry.

Major technological changes lie ahead to manufacture wafers, solar cells and modules at a cost significantly below 1 euro/Wp.

Take the Imec roadmap, for example, where the target is to reduce the quantity of pure Si needed per Wp by combining efficiencies beyond 20% with reductions in wafer thickness. It is foreseen that the industry will gradually move to back-contact solar cells, which may eventually become as thin as 80 or even 40 µm if novel techniques to realise and handle such thin Si foils become available.

But engineering these cells of the future implies that contamination issues, control of doping profiles and the introduction of new materials be reconsidered, taking advantage of the process knowledge associated with IC manufacturing.

An example is the need for improved surface passivation techniques that give us sub-nm control. Traditional passivation schemes for Si solar cells - based on silicon nitride - are not good enough for cell types with efficiencies much above 20%.

A promising solution is to deposit negative charge dielectrics such as AI₂O₃ by means of atomic layer deposition (ALD). In addition, very efficient cleaning methods will be needed to reduce metal contamination. This will allow researchers to maintain and increase the lifetime of the minority carriers in future thin Si cells.

To reach the ultimate in cell performance, it must be possible to control the dimensions of the doping profiles. With traditional diffusion-based doping, attaining this level of control for shallow emitters is not obvious. Ion implantation with its excellent areal uniformity gives a good alternative.

By using electroplated Cu the need for Ag in the metallisation can be avoided.

Replacing Ag by Cu not only decreases the cost, it can also improve the cell’s current and open circuit voltage. But the use of Cu requires a diffusion barrier that prevents the metal from diffusing into Si. The experience with barrier technology built up within the CMOS community can be a good starting point.

All these examples suggest that processes can be copied from CMOS manufacturing into PV lines. But does this make sense? The answer is: definitely not. The throughput of techniques such as ion implantation and ALD is much too low and the cost of most of these techniques is way too high for use in the PV industry.

Rather, researchers must look at how the CMOS knowledge and techniques can be adapted to the benefit of the PV community. The CMOS toolbox must be solarised - in view of this one objective: reducing the euro/Wp.

The first steps in this direction have already been taken. Equipment manufacturers are coming up with new solutions and the first solar cells made with new process steps like Cu metallisation and ALD-based surface passivation look promising.

Imec

www.imec.be