Cheaper solar cells around the corner?

Imec is a non-profit European research organisation specialising in the study of nanoelectronics, using the expertise of its global partners in ICT, healthcare and energy. Founded in 1984, its headquarters are in Leuven in Belgium, with offices in the Netherlands, Taiwan, the US, China and Japan. Its staff of more than 1750 includes over 550 industrial residents and guest researchers. Here are some highlights from recent research projects.

The organisation’s research into photovoltaics aims at finding techniques to fabricate cheaper and more efficient solar cells. Imec has built up a strong expertise of more than 25 years in silicon solar cell research.

It uses this know-how on a whole range of technologies, going from silicon solar cells (the bulk of today’s commercially available cells), over organic solar cells, to advanced stacks of super-efficient solar cells based on germanium substrates (to be used, for example, in satellites or solar concentrators) and germanium-based thermophotovoltaic cells.

In 2009, imec launched an industrial affiliation program (IIAP) on crystalline Si PV. As with imec’s other IIAPs in IC scaling, it defined the generic base for the research: developing technologies to reduce the cost of energy production through silicon solar cells.

Companies are invited to join imec’s Si PV IIAP to do joint precompetitive research. By bringing companies together around this program, the organisation aims to create an ecosystem with solar cell producers, material suppliers, tool suppliers and energy companies.

The cross-fertilisation between these will advance the research to new levels.

The multi-partner R&D initiative has already generated a lot of interest from industrial players. Important players such as Schott Solar, Total, GDF Suez and Photovoltech joined the Si PV IIAP last year.

Epitaxial solar cells

Imec created large-area (70 cm²) epitaxial solar cells with efficiencies up to 16.3% on high-quality substrates. Efficiencies of up to 14.7% were achieved on low-quality substrates showing the potential of thin-film epitaxial solar cells for industrial manufacturing.

The results were achieved within the solar cell industrial affiliation program that explores and develops advanced process technologies aiming at a sharp reduction in silicon use, while increasing cell efficiency and lowering substantially the cost per watt peak.

Jef Poortmans, director, imec energy/solar program, said these efficiencies show that they are within reach.

“By implementing copper-based contact schemes, we can further increase the efficiency, making epitaxial thin-film silicon solar cells on low-cost wafers an interesting industrial technology,” he said.

Spray coating

The organisation optimised its spray-coating technique resulting in organic solar cells with the same power conversion efficiency of the reference spin-coated devices, above 3.7%.

With the development of two-solvent systems for each of the materials to be deposited, imec achieved smooth and uniform polymer thin films with good optical and electronic properties via a large-area, roll-to-roll compatible technology that could replace spin coating and enable the inexpensive production of organic solar cells.

TPV research

On TPV research, imec has developed an improved processing technique for germanium-based thermophotovoltaic (TPV) cells resulting in a reduction of cell cost, an essential step to develop a market for thermophotovoltaic applications.

Newly developed TPV cells are fabricated on germanium substrates with a rough surface, instead of the traditionally used substrates with mirror-polished front surfaces.

Research partners

Micron Technology, Applied Materials and Ultratech have joined the imec industrial affiliation program (IIAP) on GaN-on-Si technology.

This multi-partner R&D program focuses on the development of GaN-on-Si (gallium nitride-on-silicon) process and equipment technologies for manufacturing solid-state lighting (eg, LEDs) and next-generation power electronics components on 8″ Si wafers.

Gallium nitride is a promising material for optoelectronics and power electronic components, offering higher breakdown voltage and current capacity than silicon.

However, to make GaN-based devices a competitive alternative, manufacturing technology needs to achieve the same economies of scale. Today, state-of-the-art LED manufacturing processes are typically performed on expensive 4″ sapphire substrates.

By depositing the GaN material on 8″ silicon substrates, the productivity of GaN-based device manufacturing can be increased.

In addition, imec’s GaN-on-Si program is using an Applied Materials mainframe to develop 8″; GaN-on-Si technology that is compatible with the CMOS fab infrastructure. This can further enhance productivity and give lower costs.

The multi-partner GaN R&D program, launched in 2009, aims to reduce the cost and improve the performance of GaN devices. This program brings together integrated device manufacturers, foundries, compound semiconductor companies, equipment suppliers and substrate suppliers to develop 8-in GaN technology. The IIAP builds on imec’s track record in GaN epi-layer growth, new device concepts and CMOS device integration.

Micron Technology, Applied Materials and Ultratech will actively participate in the IIAP at imec in Leuven, Belgium. This on-site participation enables the partner companies to have early access to next-generation LED and power electronics processes, equipment and technologies.

Immersion lithography

The organisation and ASML have collaborated to qualify ASML’s Tachyon Source Mask Optimisation and programmable illuminator system FlexRay, proving its potential with the demonstration of a 22 nm SRAM memory cell.

The ASML XT:1900i lithography scanner at imec is being equipped with FlexRay, enabling further exploration of the frontiers of immersion lithography.

A key part of any optical lithography system is the illuminator. It creates the pupil shape, ie, the condition and shape of the light beam before it hits the mask. By tailoring the pupil shape to the specific layout to be printed, the resolution and process margins can be improved.

Optimising the pupil shape is critical, especially with process tolerances reaching the limits of manufacturability.

Imec proved the potential of freeform illumination with a demonstration of double patterning into a hard mask of the contact and metal layer for a 22 nm node SRAM of 0.078 µm² bit cell area, with the application of simultaneous source and mask optimisation (ASML Brion Tachyon SMO) and imaging using FlexRay illumination.

Already from the images, but in particular from the metrics, it is clear how freeform illumination leads to a pattern quality that cannot be created using standard illumination. In this particular case, the XY asymmetric position of the freeform poles cannot be mimicked in a standard source.

Narrow pitch interconnects

The organisation has established a major step towards 20 nm half-pitch interconnects with electrically functional copper lines embedded into silicon oxide using a spacer-defined double patterning.

“We are very proud to be the world’s first in developing and processing such small on-pitch working interconnects;” said Zsolt Tokei, program director interconnects at imec.

“Spacer-defined (or self-aligned) double patterning has recently gained interest as the patterning technique for future flash memory devices. I’m confident that memory companies will benefit from this result.”

Scaling interconnects towards 20 nm half pitch faces many challenges. Double patterning lithography is needed since the metal lines cannot be created in a single print. Therefore, a solution is needed for the actual design split of the structures and the alignment of the different masks.

Filling (sub-)20 nm lines is not possible using standard physical vapour deposition of TaN/Ta-based metallisation. Moreover, control of line-edge roughness becomes increasingly difficult with further scaling and engineering of the patterning stack is required for optimal adhesion.

Imec demonstrated patterning and metallisation of 20 nm half-pitch copper lines in silicon oxide with a TiN metal hard mask. The patterning is based on a sacrificial double hard mask and uses three photos (core, trim and patch) and four etch steps. The core photo defines dense lines at 40 nm half pitch, which, after trim, etch and spacer deposition, results in 20 nm half-pitch spacer loops.

The trim makes large openings to cut the spacer loops away by etch. And patch defines the final layout, electrical connections and bond pads. Overlay control is critical to end up with the designed test pattern. The dielectric spacing between the metal lines was accurately controlled due to the spacer-defined integration method. A Ruthenium-based metallisation scheme was used to realise voidless filling.

Dielectric breakdown properties of the interconnects were measured and the results are very encouraging, as the breakdown field is close to the intrinsic dielectric breakdown properties of the oxide and dielectric cap layers.

Improved MEMS

Imec has demonstrated the value of its SiGe above-IC MEMS technology platform for improving performance of MEMS with the development of new devices.

These are a 15 µm SiGe micromirror and a grating light valve for high-resolution displays. The devices were generated with the organisation’s generic CMOS-compatible MEMS process for the monolithic integration of MEMS devices directly on top of CMOS metallisation.

The micromirror, designed for use in display systems, uses an electrostatic actuation mechanism relying on six electrodes. The design enables analog pulse-width modulation instead of the binary-weighed PWM of current MEMS-based micromirrors.

This mechanism allows display of a large range of grey-scale values, while binary-weighed PWM depends on the number of subframes or bit planes. Using analog PWM leads to higher response speed, less image processing hardware and less memory.

The analog PWM is implemented on the MEMS level instead of on the CMOS level, allowing a simplified electronic circuit.

The second device is a grating light valve, a MEMS reflection grating producing bright and dark pixels in a display system by controlled diffraction of incident light due to electrostatic deflection of microbeams.

The valve uses clamped-clamped microbeams which are suspended over an electrode. It can modulate the intensity of the diffracted light when an actuation voltage is applied to half the beams.

Display systems using such a technology provide a high contrast ratio, high resolution and high brightness. Both the mirrors and valves are created with a 300 nm thick SiGe structural layer.

Promising results have been reported in an extreme ultraviolet lithography mask-cleaning program for defect-free masks which are crucial in achieving high chip manufacturing yield.

The research program was initiated in collaboration with mask-cleaning experts of HamaTech APE GmbH & Co KG, a fully owned subsidiary of Süss MicroTec AG, and some of imec’s core partners.

The aim of the program is to develop processes of record for EUV mask cleaning that not only are effective in removing particles and organic contamination without damage to the vulnerable materials of the EUV masks, but do not reduce mask lifetime through repetitive cleaning.

A specific EUV reticle back-side cleaning process is being developed, to protect the electrostatic reticle chuck of the EUV scanner from degraded performance which can negatively affect the ‘print on wafer’ results. Project completion is targeted for the end of 2010.

Research started after a successful installation of HamaTech’s MaskTrack Pro photomask processing system at the imec 300 mm cleanroom in early 2010, close to the ASML EUV Alpha demo tool.

A combination of physical and chemical cleaning technologies has demonstrated an effective removal of organic and inorganic contamination without any negative effects on mask integrity. The vulnerable absorber and capping layer of the reticle presented no significant signs of deterioration.

imec

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