Semiconductor protection tips for 3-level topologies

Supplied by Semikron Pty Ltd on Monday, 21 October, 2019


3-level topologies are mainly used in UPS and solar applications due to their high efficiency and low harmonic distortion of the grid. Essential for the design of the driver is to limit the voltage at the IGBT and handling of short circuits.

This application note describes the control and protection of power semiconductors in 3-level NPC and TNPC topologies.

Related White Papers

Enabling Mechatronics Product Development with Digital Prototyping

This white paper features information on how Digital Prototyping enables manufacturers to...

How to fast-track the development of your electronic products

This white paper describes how the TestOps development culture can speed the overall...

Key design tips for high-performance environmental monitoring

Equipment and sensors built for environmental monitoring contend with a myriad of...


  • All content Copyright © 2025 Westwick-Farrow Pty Ltd