MathWorks Vision HDL Toolbox

Tuesday, 12 May, 2015 | Supplied by: MathWorks Australia


Vision HDL Toolbox, from MathWorks, provides pixel-streaming algorithms for the design and implementation of vision systems on FPGAs and ASICs. The device has been created to help developers prototype and implement systems faster, with shortened design cycles and more efficiently, through the ability to identify design errors early in the workflow and minimise the time needed for writing HDL code.

The toolbox includes a design framework that supports a diverse set of interface types, frame sizes and frame rates, including high-definition (1080p) video. The image processing, video and computer vision algorithms in the toolbox use architecture appropriate for HDL implementations.

The product provides a library of image processing and computer vision algorithms specifically designed for FPGA and ASIC implementation, as well as automatic conversion between frames of various sizes and pixels. When used with HDL Coder, designers can generate readable and vendor-independent HDL code from these algorithms. With HDL Verifier, designers can connect the algorithms running on the FPGA or ASIC with frame-based test models running in MATLAB or Simulink.

Online: au.mathworks.com
Phone: 02 8669 4700
Related Products

iBase AGS104T IoT gateway edge computing system

The iBase AGS104T IoT gateway edge computing system supports up to 16 GB of DDR5-4800 memory,...

Vecow RCX-3750 PEG GPU-accelerated system

The VECOW RCX-3750 PEG GPU-accelerated system is designed to handle demanding AI, edge computing...

STMicroelectronics PWD5T60 three-phase driver

The STMicroelectronics PWD5T60 three-phase driver features a ready-to-use evaluation board that...


  • All content Copyright © 2024 Westwick-Farrow Pty Ltd