Aldec Active-HDL design creation and simulation range

Active-HDL is a Windows-based integrated FPGA design creation and simulation solution that includes a full HDL graphical design tool suite and RTL/gate-level mixed-language simulator.

The design flow manager evokes 90-plus EDA and FPGA tools, during design entry, simulation, synthesis and implementation flows, making it a design creation and simulation platform that supports FPGA devices, from Altera, Atmel, Lattice, Microsemi, Quicklogic, Xilinx and more.

Features include: multiFPGA and EDA tool design flow manager; graphical design entry and editing; Code2Graphics and Graphics2Code; precompiled FPGA vendor libraries; IEEE language support: VHDL, Verilog, SystemVerilog (Design), SystemC; debugging and code coverage; IP encryption and Xilinx secure IP support; ABV, assertion-based verification (SVA, PSL, OVA); DSP Co-simulation with MATLAB/Simulink; HTML and PDF design documentation; integration with Riviera-PRO and ALINT; HDL code analysis and navigation tool; IP Encryption, Altera IP and Xilinx Secure IP support.