Renesas 5DB0148 DDR5 data buffer

Renesas Electronics has announced a high-speed, low-power DDR5 data buffer for data centre, server and high-performance workstation applications.

Advancements over the past few years in real-time analytics, machine learning, HPC, AI and other memory and bandwidth-hungry applications have fuelled growth in server memory bandwidth requirements. The JEDEC-compliant DDR5 data buffer, named 5DB0148, is designed to enable higher speeds and lower latency for the load-reduced dual inline memory modules (LRDIMMs) that have become the cornerstone memory technology for this class of applications. High performance will also be enabled for alternative high-density modules and heterogeneous memory solutions.

The data buffer maximises channel eye opening for systems that are heavily loaded through a combination of capacitive load reduction, data alignment and signal recovery techniques. This allows server motherboards with a large number of memory channels and slots and complex routing topologies to run at maximum speed, even when fully populated with high-density memory. Additionally, improvements in the DDR5 modules definition allow for lower power supply voltages (1.1 vs 1.2 V in DDR4), on-DIMM voltage regulation and implementation of advanced control plane architectures with the use of the SPD Hub and modern control bus communications such as I³C.

The data buffer is optimised to work seamlessly with the other DDR5 Renesas components on an LRDIMM memory module, including the power management IC P8900, the registered clock driver 5RCD0148, the SPD Hub SPD5118 and the temperature sensor TS5111. Memory vendors deploying the company’s chipset solutions should expect full interoperability and robust quality.