2D ferroelectric transistor to enhance memory storage tech

Researchers from Tokyo Tech have developed a novel ferroelectric semiconductor memory to advance memory storage technology. It has the potential to open novel data storage and processing capabilities, paving the way for faster and more energy-efficient devices.

Traditional memory technologies face limitations in terms of speed, scalability and power consumption, making them unsuitable for future data-intensive applications. Ferroelectric memory has gained interest in recent years due to its potential for non-volatile storage, enabling data retention even when the power is turned off. The development of two-dimensional (2D) van der Waals material α-In₂Se₃ has also presented new opportunities for advancing memory technologies.

Ferroelectric memory has taken a step forward by incorporating the properties of α-In₂Se₃. It is renowned for high carrier mobility, tuneable bandgap and strong ferroelectric properties at the atomic level, making it suitable for high-speed memory applications. However, the scope of research is limited due to the lack of α-In₂Se₃ devices that demonstrate in-plane (IP) polarisation-controlled electrical characteristics. When fabricating bottom-contact ferroelectric field-effect transistors by 2D material exfoliation, wide electrode width is preferred to improve the overall yield. However, achieving nanoscale channel lengths for the nanogap electrodes is challenging when simultaneously employing wide electrode widths, due to the substantial ratio between the electrode width and the channel length.

The researchers, led by Professor Yutaka Majima from the Tokyo Institute of Technology, proposed a new concept of bottom contact structure at the nano level to solve this problem. They designed a ferroelectric semiconductor memory device with a two-terminal nanogap-structured bottom contact by leveraging the IP polarisation flipping of α-In₂Se₃. The research findings are published in Advanced Science.

Distinct from previous devices, α-In₂Se₃ is exfoliated on electrodes as the bottom contact in the present design. The IP polarisation can be reversed by applying a drain voltage via a channel with a narrow length of 100 nm. This lateral channel design allows for higher memory density, enabling the integration of many memory cells on a single chip. The lateral memory configuration used in the proposed technology enables seamless integration with existing semiconductor device fabrication techniques, facilitating a transition from current memory technologies to non-volatile ferroelectric memory.

The α-In₂Se₃ ferroelectric memory exhibited typical resistive switching, a high on/off ratio of over 103, a large memory window of 13 V, good retention for 17 hours and endurance for 1200 cycles. This could pave the way for non-volatile ferroelectric memory. Massive integration is also likely with a bottom contact structure, considering the simplified construction of next-generation electronics.

Majima said the ferroelectric semiconductor memory cultivates the IP polarisation α-In₂Se₃ from a 100 nm bottom contact design, representing a leap forward in memory technology. “We believe that this design will pave the way in which data is stored and accessed and open up exciting opportunities for various applications, including artificial intelligence, edge computing and Internet of Things devices,” Majima said.

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