Renesas RH850/U2B cross-domain microcontrollers

Renesas Electronics introduces a powerful group of microcontrollers (MCUs), designed to address the growing need to integrate multiple applications into a single chip and realise a unified electronic control unit (ECU) for the evolving electrical–electronic (E/E) architecture.

Delivering a combination of high performance, flexibility, freedom from interference and security, the cross-domain RH850/U2B MCUs are built for the rigorous workloads required by vehicle motion in terms of hybrid ICE and xEV traction inverter, high-end zone control, connected gateway and domain control applications. Users can also combine the MCUs with Renesas’s R-Car S4 system-on-chip devices for automotive central gateway systems to build a scalable solution for E/E architectures.

The MCUs offer high levels of performance, memory integration and hardware-based support for zone- and domain-control applications, particularly for powertrain and HEV/EV. This combination enables users to integrate multiple ECU functions into a single ECU while adhering to stringent automotive-grade safety, security and real-time operation requirements.

The MCU’s integrated hypervisor hardware-based virtualisation assist function allows multiple software systems with up to ISO26262 ASIL D functional safety levels to operate independently, without interference, during high performance, and reduces the virtualisation overhead to maintain real-time execution. Quality of service (QoS) provides a latency monitor and regulation function for all bus masters so that minimum bandwidth is always available.

The MCUs support safe and rapid full no-wait OTA software updates with dual-bank embedded flash that allows the ECU to update and save images while the MCUs are in active mode and enables the ECU to operate from the original code if a failure occurs. Integrated motor control accelerator IP (EMU3S) works in conjunction with multiple dedicated motor control timer structures like GTM v4.1 and TSG3 to reduce CPU processing loads while achieving high-speed rotation. Dedicated data flow processor (DFP) accelerator IP enables the CPU to offload compute-heavy operations for complex control.