Triple-Gate transistor from research to development

Intel has announced details of its 'tri-gate' transistor design, stating that the tri-gate transistor is moving from research to the development phase.

The 3D transistor's structure is like a raised plateau with vertical sides, which allows electrical signals to be sent along the top of the transistor gate and along both vertical sidewalls. This effectively triples the space available for electrical signals to travel, like turning a one-lane road into a three-lane highway, but without taking up more area.

Fast transistor are one of the key building blocks of high -performance microprocessors. Since originally announced last year, Intel researchers have shrunk the size of the tri-gate transistor (measured by the gate length) from 60 to 30 nm. Transistors with a smaller gate switch on and off faster, ultimately enabling faster microprocessors.

"Our latest research indicates that the scalability, performance and excellent manufacturability of our tri-gate transistor makes it a strong contender for the production as early as 2007 on our 45 nm process technology," said Sunlin Chou, senior vice president and general manager of Intel's Technology and Manufacturing Group. "The results place non-planar, 3D transistor structures among the promising nanotechnology innovation that we will use to extend silicon scaling and Moore's Law well into the future."

The transistor is designed so that it can be manufactured in high volume, and it also addresses the growing current leakage problem that the industry faces as CMOS devices are made ever smaller. The tri-gate transistor's leakage is far less than of a planar transistor of the same size.