Plans for multicore benchmarks unveiled

The Embedded Microprocessor Benchmark Consortium (EEMBC) has announced plans to roll out new benchmarks that will address multiprocessing systems, multicore processors and multithread processors.

The EEMBC effort, which has been underway since mid-2006, is being led by John Goodacre of ARM, who serves as chair of EEMBC's multiprocessing workgroup.

With the proliferation of multicore processor implementations, the need is growing for performance benchmarks that can give an accurate indication of the value of transitioning from a single-core to a multicore system, in addition to determining the impact of system-level bottlenecks, such as those encountered when moving data on and off a multicore chip.

EEMBC is addressing this challenge with multicore benchmark suites that will enable standardised evaluation of the benefits of concurrency while providing the scalability needed to support any number of multiple cores.

The benchmarks will target three forms of concurrency, including task decomposition, multiple data stream processing and the processing of multiple workloads.

To implement this strategy on the benchmark level, EEMBC is developing a test harness that will communicate with the benchmark through an abstraction layer that is analogous to an algorithm wrapper. This test harness will provide a flexible interface to allow a wide variety of thread-enabled workloads to be tested.

In addition to using some of the existing EEMBC benchmarks in its multicore-enabled benchmark suites, EEMBC has begun work on multicore-capable VoIP and H.264 benchmarks.