Novel scheme to fabricate Ge virtual substrates

IMEC has used selective epitaxial growth and chemical mechanical polishing to obtain Ge virtual substrates with low threading dislocation density.

With this fabrication, high-quality Ge virtual substrates for pMOSFET devices as well as for selective epitaxial growth of III-V materials for creating nMOSFET devices can be provided.

The downscaling of CMOS devices requires new channel materials with high carrier mobility, such as high hole mobility Ge and high electron mobility III-V materials.

These materials have already been integrated on shallow trench isolated Si substrates by using SEG. But despite many efforts, this has so far resulted in a high threading dislocation density, causing degradation of device performance.

By combining SEG and CMP, IMEC presents a novel fabrication scheme that allows the formation of Ge virtual (ie on top of Si) substrates with low threading dislocation densities. The process comprises a selective growth of Ge on STI patterned wafers, followed by an ex-situ annealing of the Ge layer at 850 °C to reduce the threading dislocation densities.

After the post-growth anneal, Ge is polished back to the STI surface leaving about 300 nm Ge layers in the STI trenches.

The threading dislocation densities in trenches of different sizes (ranging from 0.15 to 10 µm) are confirmed to be down to 1x10⁷cm^-2. After CMP, the Ge layers have an RMS roughness of 0.15 nm.

The uniform and low threading dislocation density in these Ge layers provides the feasibility of fabricating high-quality Ge virtual substrates containing 250-300 nm thick Ge layers with smooth surface.

Since these layers are obtained for both wide and narrow (sub-micron) trenches, the fabrication approach is not mask dependent and hence compatible with IC manufacturing for different applications.

The substrates will allow the fabrication of Ge pMOSFET devices as well as the selective epitaxial growth of III-V materials (such as InGaAs) for creating nMOSFET devices.

The key mechanisms responsible for the reduction of the threading dislocation density have also been investigated. It was found that after annealing the Ge surface at 850 °C, a threading dislocation glide and reaction occurs, which leads to the formation of a confined dislocation network about 50 nm above the Ge/Si interface.

The resulting strain field around each dislocation is believed to be responsible for the formation of crosshatch patterns. Therefore, the formation of crosshatch patterns on annealed Ge layers indicates a reduction in threading dislocation density.

With CMP, the crosshatch patterns can be easily removed and a smooth surface is obtained.