New manufacturing technique for microelectronics

Thursday, 24 July, 2003

About every 18 months, the number of transistors in computer chips doubles - the direct result of ever-shrinking sizes. By decreasing the size of these components and consequently, fitting more of them onto a single chip, computer speed and power improves. Thanks to a new manufacturing technique - developed by an international team of researchers which includes Paul Nealey, a University of Wisconsin-Madison chemical engineer - manufacturing the minute may soon be cheaper and more exact.

The standard manufacturing method used to develop tiny devices inside computer chips uses a process called lithography to build the different layers that make up microelectronic devices. However, this method is currently cost prohibitive at a smaller scale, says Nealey.

Another approach that could be used to build smaller microelectronic devices exists, but it has its own set of limitations. The method relies on long chains of molecules called block copolymers that arrange themselves into patterns on a given surface.

"With self-assembling materials, achieving dimensions of tens of nanometers is inexpensive and routine," says Nealey. But, he adds, although the method may be cheap, it can result in defects and does not meet the numerous constraints of fabrication.

By merging the principles of both techniques, researchers at UW-Madison and Paul Scherrer Institute in Switzerland developed a hybrid approach that maximises the benefits and minimises the limitations of each technique.

"Our emphasis is on combining the approaches, using the desirable attributes of both, to get molecular-level control in the existing manufacturing processes," Nealey explains.

Specifically, the team of researchers used lithography to create patterns in the surface chemistry of a polymeric material. Then, they deposited a film of block copolymers on the surface, where the molecules arranged themselves into the underlying pattern without imperfections.

The most promising application for such a hybrid technology, could be the development of magnetic storage media with nearly the maximum possible capacity per unit area. In addition, this new technology could lead to the design of new microelectronic devices with unknown potential.

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