Micron to adapt hybrid memory cube for supercomputers

Micron Technology is planning to adapt its hybrid memory cube (HMC) for petascale supercomputer systems, representing a dramatic step forward in memory technology. HMC is designed for applications requiring low-energy, high-bandwidth access to memory, which is the most important requirement for supercomputers. Other applications include data packet processing, data packet buffering or storage, and processor acceleration.

Supercomputing is a technology that enables scientists and engineers to address complex simulations that drive research and development and enables them to explore fundamental questions about the organisation of our universe.

Addressing topics of this magnitude requires tremendous data movement capability. Using HMC to unlock the potential of a supercomputer’s multicore processor architecture will enable exceptional performance efficiency.

Micron and Fujitsu are each exhibiting a display board that features HMC devices in Fujitsu”s next-generation supercomputer prototype at the Supercomputing ’13 Conference in Denver this month.

“The designers and engineers at Fujitsu saw early on the value of raising their system to the next level with the help of Hybrid Memory Cubes,” said Brian Shirley, vice president of Micron’s DRAM Solutions Group. “We anticipate helping Fujitsu to immediately grow their capabilities for the most advanced computing challenges.”

“Our system designers are highly impressed with HMC because it enables new memory system designs that support our increased demand for bandwidth, super-compact form factor and optimised energy per bit,” said Yuji Oinaga, head of Fujitsu’s Next Generation Technical Computing Unit.

“For optimal performance efficiency of the application software, it is essential to improve the B(Bytes)/F(Flops) ratio, and HMC represents the new standard in memory performance for supercomputing.”

An industry breakthrough, HMC uses advanced through-silicon vias (TSVs) - vertical conduits that electrically connect a stack of individual chips - to combine high-performance logic with Micron’s state-of-the-art DRAM. Micron’s HMC delivers an unprecedented 160 GBps of memory bandwidth while using up to 70% less energy per bit than existing technologies, which dramatically lowers customers’ total cost of ownership (TCO).

Micron expects volume production of both the 2 GB and 4 GB HMC devices later in 2014.