Low-power tunnelling transistor for high-performance devices

Researchers from Pennsylvania State University (Penn State), the National Institute of Standards and Technology (NIST) and wafer company IQE have written a paper on recent developments in compound semiconductor device technologies for high-speed and low-voltage/low-power applications.

The paper describes the feasibility of a new type of transistor that could make possible fast and low-power computing devices for energy-constrained applications such as smart sensor networks, implantable medical electronics and ultramobile computing, thus enabling the Internet of Things. Called a near broken-gap tunnel field effect transistor (TFET), the device uses the quantum mechanical tunnelling of electrons through an ultrathin energy barrier to provide high current at low voltage.

TFETs are considered to be a potential replacement for current CMOS transistors, as device makers search for a way to shrink the size of transistors and pack more into a given area. The main challenge facing current chip technology is that as size decreases, the power required to operate transistors does not decrease in step. The result is batteries that drain faster and increasing heat dissipation that can damage electronic circuits.

Various new types of transistor architecture using materials other than the standard silicon are being studied to overcome the power consumption challenge. Penn State graduate student Bijesh Rajamohanan, the lead author of the study, said a new transistor had “previously been developed in our lab to replace MOSFET transistors for logic applications and to address power issues”.

“In this work we went a step beyond and showed the capability of operating at high frequency, which is handy for applications where power concerns are critical, such as processing and transmitting information from devices implanted inside the human body.”

The researchers tuned the material composition of the indium gallium arsenide/gallium arsenide antimony so that the energy barrier was close to zero - or near broken gap, which allowed electrons to tunnel through the barrier when desired. To improve amplification, the researchers moved all the contacts to the same plane at the top surface of the vertical transistor.

The research was conducted as part of the National Science Foundation-supported Nanosystems Engineering Research Center (NERC) for Advanced Self-Powered Systems of Integrated Sensors and Technologies (ASSIST). The paper was presented at the International Electron Devices Meeting (IEDM) in Washington, DC - a prestigious conference which addresses key topics affecting future semiconductor technologies and is attended by a global audience.

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