Fully coupled annealing processor for enhanced problem solving

Annealing processors are designed to address combinatorial optimisation problems, where the task is to find the best solution from a finite set of possibilities. This holds implications for practical applications in logistics, resource allocation, and the discovery of drugs and materials. In the context of CMOS (a type of semiconductor technology), it is necessary for the components of annealing processors to be fully ‘coupled’. However, the complexity of this coupling affects the scalability of the processors.

In a new study published in IEEE Access, researchers have developed and tested a scalable processor that divides the calculation into multiple LSI chips. The researchers, led by Professor Takayuki Kawahara from Tokyo University of Science (TUS), aimed to achieve advanced information processing directly at the edge, rather than in the cloud or performing pre-processing at the edge of the cloud. Using the unique processing architecture announced by TUS, the researchers developed a fully coupled LSI (large scale integration) on one chip using 28 nm CMOS technology. The researchers also devised a scalable method with parallel-operating chips, and demonstrated its feasibility using FPGAs (field programmable gate arrays).

The scalable annealing processor used 36 22 nm CMOS calculation LSI chips and one control FPGA. This technology enabled the construction of large-scale fully coupled semiconductor systems following the Ising model (a mathematical model of magnetic systems) with 4096 spins. The processor incorporates two distinct technologies developed at TUS. This includes a ‘spin thread method’ that enables eight parallel solution searches, coupled with a technique that reduces chip requirements by about half compared to conventional methods. The annealing processor is also designed to operate at 10 MHz with a power consumption of 2.9 W (1.3 W for the core part). This was practically confirmed using a vertex cover problem with 4096 vertices.

The successful machine verification of this processor suggests the possibility of enhanced capacity. According to Kawahara, this technology could be developed for a joint research effort targeting an LSI system with the computing power of a 2050-level quantum computer for solving combinatorial optimisation problems.

“The goal is to achieve this without the need for air conditioning, large equipment or cloud infrastructure, using current semiconductor processes. Specifically, we would like to achieve 2m (million) spins by 2030 and explore the creation of new digital industries using this,” Kawahara said.

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