Microchip Technology ZL40292, ZL40293, ZL40294 and ZL40295 clock buffers

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Four 20-output differential clock buffers that exceed PCIe Gen 5 jitter standards for next-generation data centre applications are now available from Microchip Technology.

The ZL40292 (85Ω termination) and ZL40293 (100Ω termination) are specifically designed to meet the DB2000Q specification while the ZL40294 (85Ω termination) and ZL40295 (100Ω termination) are designed to meet the DB2000QL industry standard. All are suitable for next-generation servers, data centres, storage devices and other PCIe applications. The devices also meet PCIe Gen 1, 2, 3 and 4 specifications.

Each buffer complements chipsets where distributed clocks are required across several peripheral components, such as central processing units (CPUs), field programmable gate arrays (FPGAs) and physical layers (PHYs) in data centre servers and storage devices, along with many other PCIe applications. The devices’ low additive jitter of ~20 fs exceeds the DB2000Q/QL specification of 80 fs. This provides designers with large margins to meet tight timing budgets while achieving increasing data rates. The devices will minimise jitter when distributing clocks to up to 20 outputs, thereby maintaining the integrity and quality of the clock signal through the buffer.

The buffers are said to achieve low power dissipation and contribute savings to power budgets by using low-power high-speed current steering logic (LP-HCSL). Compared to standard HCSL, LP-HCSL consumes one-third of the power, leading to a decrease in power consumption. This feature should give users the ability to drive longer traces on their board, improving signal routing while reducing components and board space. The ZL40292, for example, can eliminate up to 80 termination resistors (four per output) compared to traditional HCSL buffers.

The ZL40292 and ZL40293 are available now in 72-pin 10 x 10 mm QFN packages. The ZL40294 and ZL40295 are available in 80-pin 6 x 6 QFN packages.