Stable patterned electrets for microsystem applications

Imec and the Holst Centre have developed stable patterned electrets with feature sizes at least down to 20 µm. The technology consists of creating a charged profile in an SiO₂/Si₃N₄ structure by exploiting the difference in energy between the charge traps in either layer and at their interface. Patterned electret layers can be used for a plurality of technical applications such as micromotors, sensors, actuators and energy scavengers.

An electret in its most general meaning is a dielectric material that stores a quasi-permanent electric charge on its polarisation. For a plurality of MEMS applications such as micromotors, transducers and vibration energy scavengers, thin patterned electret layers are required.

In these applications, the patterned electret could serve as a high-voltage source with a service life of hundreds of years to replace both the battery and the high-voltage upconverter.

However, no technologies have so far allowed the fabrication of stable patterned electret structures with sizes of a few tens of micrometres.

Electrets patterned by using photolithography show rapid charge decay in narrow patterned structures.

Imec and Holst have now demonstrated a technology that allows the fabrication of narrow lines and other electret film structures with feature sizes down to 20 µm. The patterned electret structures show no dependence of charge retention on line width as measured one year after fabrication.

The technology makes use of an SiO₂/Si₃N₄ electret in which a charged profile is created based on the difference in energy between charge traps located in either layer and at their interface.

Stability of charge retention in electrets is related to the charge trap energy: the higher their energy, the longer is the lifetime of charge in electrets. Measurements performed by imec and Holst have shown that interface traps are much deeper than traps observed in either SiO₂ or Si₃N₄.

This feature allows the creation of a charge pattern in electrets by selective patterning the first or the second layer eg, by dry etch.

Before patterning, the electrets are protected from the ambient humidity by dehydration of SiO₂/Si₃N₄ and subsequent treatment with vapour hexametildisilazane (HMDS) at 140°C.

The developed process can be used in different microsystem applications. Furthermore, microsystems require packaging, wafer stacking and other high-temperature processes.

The technology allows such processes with practically no loss in charge and with no effect of high-temperature processes (up to 450°C) on charge retention.

It has already been used for fabricating an electrostatic energy harvester.

Further improvements focus on the development of stable electret patterns with feature sizes down to 1 µm, high-potential electrets and improved charge retention in electrets in photolithographic processes.

Junctionless transistor

The nanowire pinch-off field effect transistor or junctionless transistor is a uniformly doped nanowire without junctions with a wraparound gate. The idea and basic working principle of the nanowire pinch-off transistor were developed in imec and already reported in 2007 and 2008.

Recent modelling results obtained in imec for a GaAs and Si nanowire indicate that the nanowire pinch-off FET can outperform the nanowire MOSFET.

These results combined with scalability and ease of processing make the junctionless transistor a true competitor for the nanowire MOSFET.

Several years ago, imec theoreticians developed the concept of the pinch-off nanowire FET. Originally, the idea was to avoid surface interactions such as surface roughness scattering or high-k surface phonon scattering which degrade the charge carrier mobility, by moving the charge carriers away from the interface between the substrate and the insulator.

The solution to this problem was to consider a nanowire where source, drain and channel are uniformly doped. For an n-type nanowire pinch-off FET, the charge carriers responsible for the current are delivered by the ionised donors. As the gate voltage is increased, the channel of the wire is depleted and, eventually, pinch-off will occur.

In the nanowire pinch-off FET the charge carriers responsible for the current are occupying the entire volume.

As a result, the majority of the carriers do not reside near the interface as is the case in a MOSFET. MOSFET nanowires still require abrupt junctions for their operation and scaling down the channel length more aggressively complicates the fabrication of abrupt junctions.

The nanowire pinch-off FET or junctionless transistor is not affected by the already mentioned junction problem, which makes the fabrication process much easier.

Moreover, simulation results for a GaAs and Si nanowire now show that the nanowire pinch-off FET suffers less from short-channel effects such as drain-induced barrier lowering and subthreshold slope degradation.

This makes the nanowire pinch-off FET a true competitor for the nanowire MOSFET for future technology nodes.

imec/Holst Centre