Si substrate loss measured after ion implantation

IMEC has shown that spectroscopic ellipsometry can be used to measure Si substrate loss after ion implantation. With decreasing device dimensions, the need for this kind of metrology has become more and more important.

As junction depths decrease, even a small loss of the top Si may lead to a significant loss of dopants. Therefore, the ITRS puts strict requirements on the Si loss during processing (less than 0.4 Å per cleaning step) and a Si loss control technique is a prerequisite.

Spectroscopic ellipsometry can meet this demand, as it has proved to be an accurate, fast and inexpensive technique that can track sub-nm Si losses inline, ie, during processing.

Using ellipsometry for Si substrate loss measurement is, however, not straightforward, as the technique can only be used to measure the thickness of layers, not of substrates. But on ion implantation, a damaged Si layer is created, strained with a distorted lattice or, for higher implantation energies (above 10 keV), amorphised.

Spectroscopic ellipsometry can measure this damaged layer since the layer’s optical properties, even when it is not amorphised, are different from crystalline Si and from SiO₂.

The latter is inevitably present on top of Si after exposure to air. A comparison between spectroscopic ellipsometry and transmission electron microscopy measurements has confirmed this.

The technique has been applied to measure the Si loss of wafers after B and As implantation and after subsequent exposure to an ash plasma (N₂/H₂) at 280 °C, which is typically used for photoresist strip after ion implantation.

In this case, Si loss is related to a conversion of Si to SiO₂. Si loss can then be calculated from measuring the growth of SiO₂, taking into account that 1 nm of SiO₂ consumes 0.45 nm of Si.

After the plasma treatment, the thickness of SiO₂ increased by 0.1 and 0.8 nm, while the thickness of the amorphised layer (5 nm after implantation) decreased by 0.4 and 0.9 nm for B- and As-doped Si.

The decrease of the damaged layer thickness could be attributed partially to oxidation (Si loss) and partially to the restoration of the strained lattice.

The experiments also confirm that Si loss can be minimised by using the right plasma chemistry. When a more aggressive chemistry is used (eg, a fluorine-containing plasma), Si is additionally removed from the substrate by forming volatile compounds.

To measure the total loss, SE should be combined with mass metrology, provided that it is sensitive to changes of 10 µg or less, to meet the sensitivity of spectroscopic ellipsometry.

IMEC has also made advances in tunnel diodes.

For the first time, it is claimed, Si/SiGe resonant interband tunnelling diodes (RITDs) have been fabricated using chemical vapour deposition on 200 mm wafers. Negative differential resistance devices like RITDs can augment CMOS technology.

The fabrication demonstrates the possibility of wafer-scale integration of optimised CVD-grown RITDs with CMOS, for the sub-45 nm process nodes.

In the race to keep on scaling CMOS technology, scientists zoom in on quantum tunnelling devices. These could, in principle, be scaled down to the dimensions of atoms, because only a handful of electrons is needed to operate the devices.

Resonant tunnelling diodes (RTD), one variant of these quantum tunnelling devices, is currently studied as a way to boost the performance of conventional transistors.

There are two advantages of combining RTDs with conventional transistors. First, being quantum devices, they have a much higher switching speed while using less power. And second, because they are negative differential resistance (NDR) devices, they allow building circuits with fewer components. Using RTDs, for example, it would be possible to build a comparator with six times fewer components compared to a circuit built with today’s fastest devices.

Tunnelling diodes have been used since the sixties, but only for niche applications and not integrated in CMOS circuits. There was no Si-based process that allowed mass production of RTDs and monolithic integration with CMOS transistors.

Recently, silicon resonant interband tunnel diodes (RITD) were fabricated and a 0.5 V tunnelling SRAM cell was made.

But these RITDs were grown with low-temperature molecular beam epitaxy, while the industrial processes favor chemical vapour deposition.

Now, CVD-grown Si/SiGe RITDs have been fabricated by teams at the Ohio State University, in collaboration with IMEC.

The RITDs were grown with vapor phase doping techniques with CVD developed at IMEC. The wafers used for CVD were 200 mm types, demonstrating the possibility of wafer-scale integration of optimised CVD-grown RITDs with CMOS, for the sub-45 nm process nodes.

The RITDs incorporate δ-doping planes. The room temperature performance showed peak-to-valley current ratios up to 1.85, with a peak current density of 0.1 kA/cm². The CVD-grown RITDs received no post-growth annealing.