Save space by embedding capacitors into interposers

Scientists at the Tokyo Institute of Technology (Tokyo Tech) have developed a 3D functional interposer — the interface between a chip and the package substrate — containing an embedded capacitor. The team’s compact design saves a lot of package area and greatly reduces the wiring length between the chip’s terminals and the capacitor, allowing for less noise and power consumption.

Electronics have grown smaller and more compact over time, but this accelerating trend in performance and scale is bound to slow down as the materials and designs we use approach their physical limits. Indeed, over the last decade, progress in an essential passive component in electronics — the capacitor — has stagnated in some regards. Although we can fabricate much smaller capacitors than ever before, their actual capacity per unit area hasn’t been improving as much; we therefore need ways to make capacitors occupy less space while preserving their performance.

But what if we could integrate capacitors inside another element commonly used in modern circuits: the interposer? Tokyo Tech scientists, led by Professor Takayuki Ohba, have demonstrated that silicon interposers — the planar interface that holds and vertically connects an integrated chip with a circuit package or another chip — can be made into functional capacitors, thus saving considerable space and offering additional benefits. Their work was presented at the 2021 IEEE Electronic Components and Technology Conference.

In modern ‘2.5D’ packages, chips such as DRAMs and microprocessors sit atop interposers with through-silicon vias — vertical conducting tunnels that bridge the connections in the chips with solder bumps on the package substrate. Capacitors are placed on the package substrate close to the components they serve, and a connection between their terminals and those of the chip has to be made, spanning 5–30 mm. This layout not only increases the necessary package substrate area, it also causes problems such as high wiring resistance and noise due to the long interconnections.

In contrast with this design, the team at Tokyo Tech cut the middleman and directly made the interposer be the silicon capacitor. They achieved this through a novel fabrication process in which the capacitive elements are embedded inside a 300 mm silicon piece using permanent adhesive and mould resin. The interconnects between the chip and the capacitor are made directly with through-silicon vias and without the need for solder bumps.

“Our bumpless 3D functional interposer enables a notable reduction in package area of about 50% and an interconnect length a hundred times shorter,” Prof Ohba said.

State-of-the-art 2.5D package design versus 3D functional interposer design. The new interposer design with an embedded capacitor provides a notable reduction in area requirements and interconnect length, leading to lower wiring resistance and parasitic capacitance.

The researchers also managed to cleverly avoid the two most common problems of bumpless chip-on-wafer designs: warping in the wafer due to the resin and misplacement errors due to void pockets in the adhesive. Through testing and theoretical calculations, they determined their functional interposer allowed for a wiring resistance about a hundred times lower than conventional designs, as well as a lower parasitic capacitance. These features could enable the use of lower supply voltages, leading to lower power consumption.

“The chip-on-wafer integration technology we are developing will open up new routes in the evolution of semiconductor package structures,” Prof Ohba concluded — routes that are set to involve greater miniaturisation.

Top image credit: ©stock.adobe.com/au/Kuzmick

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