Novel data converters can be designed in hours

Researchers from the National University of Singapore (NUS) have invented a novel class of digital-to-analog (DAC) and analog-to-digital converters (ADC) that can be entirely designed with a fully automated digital design methodology, thanks to fully digital architecture.

Compared to traditional analog architectures and methodologies, the design turnaround time for the novel sensor interfaces is reduced from months to hours. The drastic reduction in the design effort is beneficial in cost-sensitive silicon systems, such as sensors for the Internet of Things (IoT). The novel data converter architecture also has low complexity, reducing the silicon area and hence the manufacturing cost by at least 30 times, compared to conventional designs.

Such novel data converters also exhibit what is claimed to be the unprecedented capability of gracefully degrading the signal fidelity when its supply voltage or clock frequency experience wide fluctuations. Such fluctuations are common in energy-harvested IoT sensors, being that the power harvested from the surrounding environment (eg, a solar cell) is highly erratic. In turn, this allows uninterrupted sensor signal monitoring even under unfavourable harvested power conditions, and without voltage regulation. Instead, traditional data converters suffer from catastrophic resolution degradation when the supply voltage is below its minimum rated value Vmin (or the frequency exceeds its maximum rated value), hence needing power-hungry circuits for voltage and frequency regulation.

“Our research transforms the traditionally analog and mostly manual design of data converters into fully automated digital design, reducing the silicon area by an order of magnitude and the design time by two orders of magnitude, allowing semiconductor companies to be cost-competitive while reaching markets faster,” said team leader Associate Professor Massimo Alioto.

“Being digital, our sensor interfaces are effortlessly ported across manufacturing technologies and applications, and can be immersed in digital circuits to avoid the traditional effort required by their integration on the same silicon chip.”

The NUS team demonstrated the concept through several silicon chips implementing both DACs and ADCs with extremely low area. As an example, a 12-bit DAC manufactured in 40 nm standard CMOS technology has been demonstrated with an area equal to the diameter of a strand of human hair. Its inherent amenability for technology scaling makes it shrink by approximately another 32 times when implemented in the currently finest technology (7 nm). At the same time, the invention has been shown to enable data converters with high resolutions (up to 16 bits), while achieving design simplicity and compactness.

“Our team has introduced a new design paradigm that pushes us closer to the ultimate vision of inexpensive, technology-scalable and ultracompact IoT devices,” said team member Dr Orazio Aiello. Indeed, the NUS innovation further simplifies integrated system design, leveraging the ability to withstand very substantial voltage and frequency fluctuations, thus relaxing the accuracy requirements in voltage and frequency generation.

A conventional data converter operating at a supply voltage below its minimum rated value (or excessive clock frequency) experiences catastrophic failure, and hence fails to perform its intended function. On the contrary, the data converters invented by the NUS team exhibit graceful degradation of the resolution and signal fidelity when supply voltage or clock frequency exceeds its allowed range. As an example, a DAC designed for 1 V was demonstrated to correctly operate at half this voltage, while degrading its resolution by only 1 bit when the supply voltage is reduced by a substantial 0.3 V.

“The capability of having graceful resolution degradation under voltage and frequency overscaling suppresses the need for complex circuit solutions that accurately regulate the supply voltage and the clock frequency being utilised by data converters,” Assoc Prof Alioto said. “In other words, our data converters are simpler to design, and also simplify the system that they are employed in.”

The team is currently working on a novel paradigm that turns traditionally analog and design-intensive silicon subsystems into digital standard cell-based designs that are supported by fully automated design flows, pushing the boundary of classical digitally assisted design. Their study involves several fundamental subsystems such as amplifiers, oscillators, voltage and current references, among others.

The team ultimately aims to transform the way integrated systems are designed, enabling ultrarapid, ultracompact and technology-portable design of entire systems.

Pictured: Dr Orazio Aiello and Associate Professor Massimo Alioto. Image credit: National University of Singapore.

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