Memory roadmap shows the way

Semiconductor manufacturers are busily trying to anticipate what the future market will demand of them, especially in that all-important field of memory. Toshiba is just one company that is looking into the future and it has outlined what it sees in its latest 'strategic memory roadmaps'.

The map reflects the company's continued focus on the rapidly-growing file storage market, the mobile electronics memory market and high-performance solutions for networking and digital consumer applications.

The company's current line-up of memory products serving these three markets includes NAND Flash, high-density NOR Flash, low-power SRAMs, Pseudo SRAMs and advanced Multi-Chip Packages which integrate various memory technologies into a single package; and for the networking and extreme performance digital consumer market, Network Fast-Cycle RAMs (Network FCRAMs) and XDR DRAM.

File storage

NAND Flash memory continues to be one of the fastest growing semiconductor products, as continuing increases in density and improving cost per bit fuel strong demand for NAND Flash as a memory choice for a wide range of file storage applications, including digital still and video cameras, USB drives, audio players, PDAs, solid-state disk drives and PC cards.

Toshiba expects the market for NAND Flash to see a 30% annual growth to 2007.

The company recently announced that it is migrating NAND Flash production to the 90 nm process, which enables the company to introduce what it claims is the industry's first 4 Gb multi-level cell NAND Flash memory, as well as a stacked, dual-die 8 Gb device.

These chips provide nearly twice the memory capacity of conventional chips of the same size by storing two bits per cell.

Also developed has been faster MLC NAND Flash by increasing the block size and optimising the memory control function in the chips.

A 16 Gb MLC NAND Flash device combining four 4 Gb die in a single package, is just round the corner.

To help meet the rapidly growing demand for NAND Flash, Toshiba started construction in April on a $2.5 billion, 300 mm fab that is expected to come online in the second half of next year with an initial output capacity of 10,000 wafers a month, growing to 37,500 monthly.

Toshiba is funding construction of the building, and FlashVision Japan, a joint venture between Toshiba and its NAND Flash strategic partner, SanDisk will fund its manufacturing equipment, with each partner providing an equal share of the funds.

The roadmap for further lithography advances calls for mass production at 70 nm to start in the first half of next year at the existing 200 mm fab, and in the first half of 2006 at the new 300 mm fab. Mass production of 55 nm NAND Flash is scheduled to start in 2007.

Mobile Electronics

For mobile electronics applications, Toshiba is one of the suppliers of MCPs, which combine various memory technologies in a single small-footprint component to meet the increasingly complex memory requirements of mobile devices.

A key trend in MCP configurations is the inclusion of NAND Flash in addition to, or in place of, NOR Flash because of its significantly faster program and erase speeds which are necessary for fast data storage, especially in camera phones.

NAND Flash-based MCPs, which Toshiba also offers, including PSRAM+NOR+NAND and NAND+LPSDRAM.

To further reduce power consumption and improve memory subsystem performance in advanced 2.5G and 3G mobile phones, Toshiba plans to offer a full 1.8 V MCP device that incorporates burst mode NOR Flash, burst mode PSRAM, low-power SRAM, NAND and/or low power SDRAM.

Typical configurations demanded include PSRAM+NOR, PSRAM+NOR+NAND, PSRAM+NOR+NAND+SDRAM or NAND+SDRAM.

Earlier this year, the company announced development of an MCP, 1.4 mm thick that can stack nine layers (for example, six memory chips with three spacers). Toshiba has used process and mounting technology to shrink each memory chip to 70 µm thickness, believed to be the thinnest in the world for MCP applications, and then bond the chips together in one package by wires.

The MCP consists of a combination of memory chips, such as SRAM, PSRAM, SDRAM, NOR Flash memory and NAND Flash memory.

By using this, with a fewer number of chips stacked, it has also become possible to achieve an MCP with 1.0 mm thickness. The chip combination available in these MCPs is flexible to accommodate the performance requirements of the user and to create the most effective package.

Pseudo SRAM

The company offers PSRAM in densities from 32 to 128 Mb, a high density of this low-power memory widely used in mobile phones where the need for higher density working RAM is rapidly growing as more features and functions are implemented.

PSRAM memory chips combine a DRAM cell for high density and low bit cost with an asynchronous SRAM external interface to facilitate efficient system design.

Burst PSRAM is based on a common specification between Toshiba, NEC and Fujitsu for PSRAM devices that features burst mode function enabling fast access.

Each company manufactures and markets PSRAM products based on the common specification, called Common Specifications for Mobile RAM (COSMORAM).

Toshiba has announced a 1.8 V 128 Mb Burst Mode PSRAM for faster, low-voltage operation in next-generation mobile phones.

Looking ahead, the company says it will support up to 256 Mb at 110 nm next year.

NOR Flash

As part of the recent announcement of a full 1.8 V MCP, Toshiba is expanding its NOR Flash line-up with a 128 Mb Page/Burst NOR Flash manufactured on a 130 nm design rule.

This device complements a selection of NOR Flash in 16 to 128 Mb densities.

The roadmap calls for higher density 256 and 512 Mb products with the migration to 90 nm in 2005.

The company's current low power SRAM range is manufactured on a 150 nm design rule, with densities of 4, 8 and 16 Mb in various speeds and input voltages from 1.8 to 5. The product map calls for progression to 130 nm later this year.

Network FCRAM

For the communications market, there is a family of Network FCRAM that combines DRAM densities with random cycle performance approaching that of high-speed SRAM to provide high performance for high-speed networking, routers, switches, and internet servers.

Network FCRAM features a short bus turnaround time, fast random access and cycle time, and a simple and consistent protocol, with a simplified command set.

A variety of products is available.

Network FCRAM has been supported since the end of 1999 and has enjoyed growth in design over the past year as a low cost, high performance replacement to high-speed SRAM and DDR SDRAM for look-up table and buffer memory.

Current devices are manufactured on a 130 nm design rule and support random cycle times down to 20 ns and data transfer rates up to 666 Mbps.

Next-generation devices will use a 110 nm process and will offer higher data transfer rates and higher densities reaching 1.152 Gb in 2006 at 90 nm.

XDR DRAM

Late last year, Toshiba was the first manufacturer to sample 512 Mb XDR DRAMs with a data transfer speed of 3.2 GHz, claimed to be the world's fast speed of any memory device. These DRAMs are based on Rambus' XDR memory interface and offer octal data rates, which transfer eight data blocks per clock cycle and offer eight times the bandwidth of today's best PC memory.

XDR DRAM is targeted for use in next-generation, high-performance broadband applications, including digital consumer electronics, network systems and graphic systems which are expected to require very high density, ultra-high-speed memory chips.

Initial product samples were developed on 130 nm process and shrink 110 nm product is already under development for volume ramping in 2005. The company plans to migrate to a 90 nm process in 2006, when the market for these emerging devices is expected to expand further.

X Architecture SOC Cadence Design Systems and Toshiba have launched what they claim is the industry's first commercial system-on-chip (SoC) devices built on the X Architecture design - a new approach to large-scale integration that enables the production of smaller, faster chips. Toshiba's latest TC90400XBG chip validates the benefits of the X Architecture by delivering a compact and highly integrated device for next-generation digital video broadcast and multimedia home-entertainment applications. The X Architecture is a way of orienting a chip's microscopic interconnect wires with the pervasive use of diagonal routes, in addition to traditional right-angle 'Manhattan' routing. This results in chip designs with fewer wires and vias to connect the wiring layers in SoC devices. By enabling higher quality device performance metrics, the architecture will bring advantages to next-generation digital media and other consumer applications. Toshiba and Cadence have collaborated on developing the architecture and are co-sponsors of the X Initiative, a consortium of more than 40 companies dedicated to facilitating the commercial adoption of the X Architecture by preparing the design chain for volume production. Toshiba's TC90400XBG chip is designed for integration in digital-media and home-entertainment applications and is fabricated with 130 nm process technology. Compared with equivalent Toshiba products with the conventional Manhattan design, the latest chip implementing the architecture is about 11% faster in speed and 10% smaller in random logic area. Mass production is expected to begin in the second quarter of 2005. The X Architecture, the first production-worthy approach to the pervasive use of diagonal interconnect, reduces the total interconnect, or wiring, on a chip by more than 20% and via-counts by more than 30%, resulting in simultaneous improvements in chip performance, power and cost. For the past 20 years, chip design has been primarily based on the de facto industry standard Manhattan architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45° from a Manhattan architecture. The architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores by preserving the Manhattan geometry of metal layers one to three.