LDMOS takes on the power supply

RF LDMOS (RF laterally diffused MOS), now referred to as LDMOS, is the dominant device technology used in high-power wireless infrastructure power amplifier applications for frequencies ranging from less than 900 MHz to 3.8 GHz.

LDMOS began to be widely deployed in high-power cellular infrastructure PA applications in the early 1990s. This device technology offers advantages over the previous incumbent device technology, the silicon bipolar transistor, including superior linearity and efficiency, high gain, and compatibility with low-cost packaging platforms.

Within a few years, LDMOS became the dominant technology and essentially displaced silicon bipolar transistors. LDMOS technology has continued to evolve to meet the ever-more demanding requirements of the cellular infrastructure market, achieving higher levels of efficiency, gain, power and frequency.

The LDMOS device structure is highly flexible. Although the traditional cellular infrastructure market has been focused on 28-32 V, Freescale Semiconductor has been developing 50 V versions of 28 V platforms for many years. Several years ago it focused its 50 V development on applications outside the cellular infrastructure market, including the industrial, scientific and medical, broadcast and radar markets, where higher power density and compatibility with commercial 48 V DC supplies are key competitive advantages.

Many of the same attributes that led to the displacement of bipolar transistors from the cellular infrastructure market in the early 1990s are equally valued in the broad RF power market - high power, gain, efficiency and linearity, low cost and outstanding reliability. In addition, the market demands the very high RF ruggedness capability that LDMOS can deliver.

The initial 50 V products designed by the company fabricated using what is known as the very high voltage 6th generation (VHV6) platform. This article will describe the VHV6 device structure, including advantages over other device technologies.

Figure 1 depicts a cross-section of a single finger of a typical LDMOS transistor.

Figure 1: Cross-section of an LDMOS device.

It includes a source metal region to electrically connect the N+ source to the P+ sinker, which in turn is connected to the back side source metal through the P+ substrate.

This lowers the source inductance to improve performance but also allows the die to be directly attached onto an electrically and thermally conductive package flange to accommodate low-cost packaging platforms.

The boron p-type ‘PHV’ diffusion establishes the threshold voltage and turn-on characteristics of the device. The WSi/polysilicon gate provides a low gate access resistance, important for the large dimensions typical of RF power devices.

A low doping concentration arsenic n-type ‘NHV’ drift region between the gate and the highly doped N+ drain region is designed to support high breakdown voltages, low on-state resistance (R_DSon), and good hot carrier injection reliability.

The stacked aluminium drain metal is designed to meet electromigration specifications for high reliability. A metal-2 gate bus running parallel to the gate makes periodic connections to the gate WSi/polysilicon stack to reduce its resistance.

Grounded shield structures (the ground strap is not shown in this figure) are also employed to reduce feedback capacitance between the drain and gate, and to control surface electric fields to allow for improved device performance without sacrificing breakdown voltage or HCI margin.

Another company innovation pioneered in the cellular infrastructure market that is incorporated into the 50 V portfolio is an enhanced ESD protection structure that can tolerate moderate reverse-bias conditions being applied to the gate lead (see Figure 2).

Table 1: Comparison of RF power attributes vs device technology.

An example of when this enhanced device is very beneficial is Class C operation at high input RF power levels. The RF swing could easily turn on a standard ESD structure during a small negative voltage swing, while the enhanced ESD device remains off.

The enhanced structure employed in the RF products is much more robust against a broad range of operating conditions that may be encountered during operation.

The primary competitive technologies in this market are the silicon VMOS (vertical MOS) device and, to a lesser extent, 28 V LDMOS. Compared with the LDMOS device, which is primarily a laterally fabricated device, the VMOS device has a significant vertical component to achieve the appropriate breakdown voltage.

Vertical dimension and doping level control is inherently limited compared to surface or horizontal fabrication; vertical structures typically rely on silicon epitaxy for both doping and thickness control, whereas lateral structures can use the deep sub-µm photolithography capability in modern fabs, while doping is determined with a high level of precision using ion implantation techniques (the same advanced techniques used in leading-edge CMOS technologies).

A performance comparison of these three technologies (VMOS, 28 V LDMOS, and 50 V LDMOS) is shown in Table 1 using various metrics that are important for success in the RF power market.

Figure 2: I-V characteristics of a standard and enhanced ESD protection device.

The colour coding is red = poor, yellow = neutral, and green = strength.

The scale ranges from 1 to 5, with 5 being highest or best. Starting down the metric list, LDMOS has superior gain and efficiency that can be traced to developments originally driven by the cellular infrastructure market where these parameters have long been of paramount importance, along with device structure advantages such as deep sub-µm self-aligned gates and shields to reduce feedback capacitance.

The LDMOS devices have thermal resistance benefits as a result of having a backside source that can be connected directly to the thermally and electrically conductive package flange, which in turn is directly mounted to the heat sink.

Typical VMOS devices have the drain on the backside of the wafer and require attaching the die to an electrically isolating flange material which increases the effective thermal resistance of this device structure.

The thermal conductivity of the LDMOS packaged products allows them to achieve higher CW power levels in a given package, especially the 50 V technology with its inherently higher power density compared to the 28 V variant.

In addition, 50 V LDMOS typically has 35% less output capacitance per W than 50 V Si technologies, making it ideal for broadband applications.

LDMOS products are typically manufactured with integrated matching networks, making the availability of on-die passives (inductors, capacitors) LDMOS strength. The lateral nature of the LDMOS manufacturing flow uses fab processes that can be controlled to very high precision levels, compared with VMOS that requires less well-controlled processes such as silicon epitaxy to form certain critical active regions of the structure, increasing variability and performance spread.

Although VMOS and LDMOS are mature technologies, the 50 V LDMOS variant is a relative newcomer to the RF power market.

Finally, LDMOS has a demonstrated track record of providing outstanding reliability with nearly 20 years of widespread deployment.

Several trends have emerged over the past few years.

The first is increased frequency of operation, with products already qualified for operation up to 3.8 GHz for 28 V. The company’s next 50 V platform will support products with frequencies exceeding 3 GHz.

The second trend is the release of high-power multi-stage ICs or discrete devices with integrated input and output matching networks.

These high-power RF devices are common in the cellular infrastructure market.

Products are in development for the RF power market that include integrated matching networks to simplify ease of use while maintaining broadband performance.

The third major trend is the adoption of over-moulded plastic for high-power RF applications. OMP is the lowest-cost packaging technology available. Package development continues, with the primary emphasis on increasing the power level that can be accommodated.

The final trend is to continue to invest heavily in 50 V LDMOS development for the RF power market.

Ruggedness failure in MOSFETs is catastrophic thermal failure of the device due to internal power dissipation. They do not occur as a result of normal operation within a power amplifier designed according to established RF design and mechanical engineering principles.

The ruggedness failure of the MOSFET is the result of a drain breakdown (impact ionisation) event. This occurs due to the distribution of charges internally within the MOSFET which are driven by the intrinsic gate and drain terminal waveforms.

Figures 3a and 3b show a generic common source PA circuit using a MOSFET and a more detailed schematic diagram of a MOSFET.

Figure 3a and 3b: Common source PA and MOSFET schematic.

There are three basic ruggedness failure mechanisms that occur as a result of a drain impact ionisation event which can result in extremely high power dissipation within the MOSFET and the associated thermal damage - and all of these mechanisms are illustrated by the diagram in Figure 3b.

The first two mechanisms involve the basic breakdown of the MOSFET drain junction - either laterally across the channel or vertically across the drain to source junction isolation.

The third mechanism is triggered by an impact ionisation event and is the self-biasing and ‘snapback’ of the parasitic bipolar device - a drain ionisation event being a necessary precondition to this behaviour.

If sufficient internal MOSFET power dissipation occurs from one of these ionisation events which exceeds the normal thermal design of the device, catastrophic device failure can be the result.

The bipolar snapback behaviour is particularly problematic as there is a positive feedback mechanism with temperature which can result in the well- documented thermal runaway phenomena for bipolar junction transistors.

RF performance, thermal characteristics, device impedances and device models focus on two categories. The first is the industrial, scientific and medical (ISM) frequency bands for VHF and UHF. Examples of ISM applications include MRI, CO₂ lasers and plasma generators.

The second category is L-band (20 cm) for pulsed radar applications such as air traffic management systems.

The company offers nine different 50 V power devices targeting the ISM band and these devices are available at different power levels and package styles.

Power levels range from a 10 W driver to a 1 kW final-stage device. Frequency ranges cover 1.8 to 600 MHz.

The MRF6VP2600H 50 V device is designed in an air-cavity ceramic package, capable of 600 W CW or can be used for pulsed applications. Because this is an unmatched device, good RF performance can be achieved across the VHF and UHF frequency bands.

The company currently has five 50 V product offerings for the radar frequency bands. These include the MRF6V10010N, MRF6V12250H, MRF6V12500H, MRF6VP121KH and MRF6V14300H devices.

The MRF6V10010N is in a low-cost over-moulded plastic package and is intended for use as a 10 W pulsed driver device, operating at frequencies from 960 to 1400 MHz.

The MRF6VP11KH can deliver 1 kW under continuous wave test signal as a result of its high efficiency and low thermal resistance.

As another example, the MRF6V12500H has been designed for the 960 to 1215 MHz frequency range. Typical performance for this 960 to 1215 MHz pulsed design gives the gain at more than 17.5 dB with better than 1 dB gain flatness and drain efficiency is greater than 56%.

The 50 V LDMOS devices have been designed for good RF performance and for good thermal performance. The ISM products have been optimised thermally for pulse applications and CW applications.

The company is producing RF LDMOS transistors to develop, qualify and release to manufacturing a portfolio of 50 V LDMOS products specifically designed for the requirements of the ISM, broadcast and commercial aerospace market segments.

The devices are claimed to provide superior power, gain, linearity and efficiency, while using cost -ffective over-moulded plastic packaging.