Australian researchers create artificial graphene

The ARC Centre of Excellence in Future Low-Energy Electronics Technologies (FLEET) has used a combination of nanofabrication techniques and conventional semiconductor materials to engineer an artificial version of graphene — one which can be manufactured on an industrial scale.

The amazing electrical properties of graphene and other 2D, atomically thin crystals are due to the symmetry of their lattice structure. For example, it is graphene’s famous ‘honeycomb’ lattice that causes electrons to act as though they were massless, moving about 70 times faster than in silicon — the semiconductor material used in most computer processors today.

But graphene and similar 2D materials faced a challenge before they could be used in any commercially viable future electronics technology: the techniques currently used to fabricate graphene are not robust or scalable enough for industrial manufacturing. With this in mind, FLEET has used nanofabrication to manipulate the surface structure of semiconductors — creating the necessary pattern at a nanometre scale to precisely recreate the electronic structure of graphene and 2D topological insulators.

Working at scales of millionths of a millimetre, such nanoengineered materials are called artificial analogues of graphene and 2D topological insulators, or simply ‘artificial graphene’. According to FLEET’s Dr Oleh Klochan, who leads the research at UNSW, the process is “not a trivial task”.

“The creation of synthetic, defect-free periodic lattices in conventional materials that successfully mimic graphene or topological insulators requires precise and accurate positioning of the lattice sites with a nanometre resolution,” Dr Klochan said.

Artificial topological systems are one of several approaches used within FLEET to achieve ‘dissipationless’ electronic transport via topological materials, which could be key to future ultralow-energy electronics.

The challenges of artificial topological insulators

In Dr Klochan’s team at UNSW, top-down processing begins with the cleanest and most extensively studied semiconductor available — a GaAs-AlGaAs heterostructure, in which scattering mean free paths exceed 100 μm.

To pattern the required artificial hexagonal lattice, the team uses high-resolution electron beam lithography. This approach allows the lattice constant of the artificial graphene to be precisely controlled, lattice defects to be controllably introduced and even local strain to be created with precision not possible in natural materials, allowing detailed tests of theories of transport in Dirac materials.

Advantages of this approach to artificial topological insulators are:

• the ease of integration with conventional semiconductor technologies;
• the ability to leverage advances in top-down fabrication of nanometre-scale structures in semiconductors;
• control of the topological properties via gate electrodes (‘switching’).
   

“By changing the bias on the gate electrode, we can switch our system from an artificial topological insulator with dissipationless edge states into a regular insulator,” Dr Klochan said.

Achieving this ‘switching’ is an important FLEET milestone, accomplishing the binary function (ie, 0s and 1s) that underlies modern electronics.

“The success of this approach will not only make it possible to control dissipationless transport with unprecedented accuracy, but chart the course for using such artificially designed topological materials for repeatable and reliable large-scale production,” Dr Klochan said.

Other advances and new facilities

A new atomic layer deposition system, supported by FLEET funding, has recently been commissioned for the project, and is now fully operational. Dr Klochan’s team has also recently developed a new fabrication technique for artificially designed materials that delivers much more uniform artificial lattices, and less damage to the host 2D system.

Fabrication comprises two critical components:

• The semiconductor transistor, which is the basis of any electronic device. The new FLEET atomic layer deposition tool is used to deposit thin gate dielectric films and improves the yield of devices dramatically.
• The artificial lattice, the ‘active’ area of the device. Electron beam lithography, at the UNSW node of the Australian National Fabrication Facility (ANFF), is used to write the pattern. Reactive ion etching (RIE) at the Australian National University (ANU) node of the ANFF is then used to transfer/engrave the pattern into semiconductor. The RIE tool is a brand new one commissioned in 2018.
   

“Because of these two machines we can now make much more superior devices,” Dr Klochan said.

Image credit: ©iStockphoto.com/Oleksiy Mark

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