Vertically stacked flash memory enhances performance

Imec is a non-profit European research organisation specialising in the study of nano electronics, using the expertise of its global partners in ICT, healthcare and energy. Founded in 1984, its headquarters are in Leuven in Belgium with offices in the Netherlands, Taiwan, the US, China and Japan. Its staff of more that 1750 includes over 550 industrial residents and guest researchers. Here are some highlights from recent research projects.

Floating gate flash memory has been scaling at a tremendous pace in recent years to arrive at a density of 32 Gb (4 GB) on a single die today, using 30 nm technology and below. Drastic device concept changes are, however, required for future generations to cope with the scaling limits of today’s floating gate technology.

For example, the electrostatic cell-to-cell interference and the low storage electron count are becoming major obstacles for further downscaling in the 20 and 10 nm range.

Stacking cells in a vertical way on a chip, hence increasing the density per unit area by eg, 8-16 for the same technology node, is a very promising approach to further push the cost down. Besides cost reduction, vertical stacking also improves the gate control and the field enhancement in the tunnel oxide because of the curvature of the gate-all-around structure.

This leads to enhanced window and drive current even in the case of a poly-Si SONOS (silicon oxide nitride oxide silicon) device.

Imec designed a new process flow and all necessary test structures to optimise the vertical transistor flow. The process flow provides a gate layer and inter-gate isolation layers, which are etched all the way down to the Si (to form the so-called ‘plug’).

Next, the ONO (oxide nitride oxide) memory gate stack is deposited on the sidewalls and the plug is filled with poly-Si, which serves as the transistor substrate.

Plug opening, bottom junction as well as top junction profile and plug fill were found to be critical steps. Cylindrical cell structures have been obtained with Si diameters down to 20 nm.

A new process has been developed to allow the removal of the ONO stack at the bottom of the plug for source junction formation without damaging the tunnel oxide on the sidewalls.

Imec’s vertical flash transistor platform will be used to investigate the scalability of this concept for the generations corresponding to the planar 1x nodes. Further experiments will include the reduction of the cell diameter, the selection of the best ONO stack taking topography into account as well as alternative channel processing schemes.

The results were obtained in collaboration with imec’s key partners in sub-22 nm core CMOS research.

Vapour sensor

An ethanol vapour sensor is fabricated using a ZnO nanoparticle film as a coating on a silicon-on-insulator (SOI) microring resonator of 5 µm in radius. The sensor can detect ethanol vapour concentrations as low as 100 ppm. This achievement demonstrates the potential of SOI technology for the development of sensitive, compact, low-power and inexpensive optical gas sensing devices.

INTEC, imec’s associated laboratory at Ghent University, and imec have coated SOI microring resonators with films of 3.5 nm ZnO nanocrystals for optical sensing of gaseous ethanol. Ethanol vapour concentrations down to 100 ppm have been detected.

The proposed technology meets today’s demand for compact, cheap, low-power and reasonably sensitive gas detection systems. By doping metal oxides with specific functional molecules, this technique can be extended for selective detection of other gases.

With this result, INTEC and imec have demonstrated the potential of SOI technology for integrated low-power and low-cost optical gas sensing. With future advancements in micropatterning techniques, other selective films can efficiently be coated on several microring resonators to achieve integrated and multiplexed multi-gas sensing on an optical chip. In several industrial, medical and environmental applications, this technology can be advantageous over other techniques (electrochemical, catalytic ...).

For instance, integrated optical gas sensors are very compact and can operate at room temperature, are suitable for remote sensing and multiplexing, are not affected by electromagnetic interference and don’t involve direct electrical contacts enabling risk-free operation in explosive gas environments.

Moreover, these sensors can provide a robust and reliable solution taking the advantage of stable metal oxide coatings. The compatibility of the SOI devices with CMOS fabrication tools and the promise of inexpensive mass fabrication make this technology additionally attractive.

The microring resonators have been fabricated with standard CMOS fabrication facilities. In practice, 193 nm deep-ultraviolet photolithography in combination with dry etching is used to fabricate high-Q microring resonators of 5 µm in radius. The local coating on the ring resonators is prepared from colloidal suspensions of ZnO nanoparticles of 3.5 nm diameter.

After coating, the SOI microring resonators have Q values of about 15,000. The porous nature of the coating provides a large surface area for gas adsorption.

When ethanol vapour is adsorbed, a change in the ZnO refractive index occurs and a shift in the resonance wavelength of the microring resonator due to evanescent field interaction can be measured, eg, exposure to 1500 ppm of ethanol leads to a shift of 500 ppm.

With this sensing configuration, ethanol vapour concentrations down to 100 ppm are detected and a detection limit below 25 ppm is estimated.

Future pMOS devices

GeSn (germanium/tin) materials show promise, for example as embedded source/drain stressors for Ge channels in future pMOS devices. Imec has started a collaboration to assess the possible applications of GeSn materials, and to see how these applications could be implemented.

First results show, among others, that GeSn (with 2-8% Sn) materials are compatible with conventional source/drain engineering processes.

One promising application of GeSn would be as stressor material for Ge channels. To outperform current uniaxial compressive strained Si channel pMOSFET technology (with embedded SiGe source/drain), it will be necessary to switch to a strained Ge channel.

A proposal is to use GeSn materials, which have a larger lattice parameter than Ge, as embedded source/drain stressors for Ge channels. An alternative would be to implement bi-axially strained Ge grown on top of a so-called strained relaxed GeSn buffer.

In addition, GeSn materials may prove interesting for photovoltaics and optical applications.

Imec, the Catholic University of Leuven (Belgium) and the Nagoya University (Japan) have started a collaboration to assess the possible electrical and optical applications of this new material and to set up a strategy to solve the challenges of material implementation. Within the frame of this collaboration, imec examines the epitaxial growth and material properties of (Si)GeSn. The collaboration is supported by a joint JSPS-FWO project, which started in April.

Simulation results show that a minimum of 5% Sn is required in the GeSn source/drain to build a strained Ge pMOSFET that is competitive with strained Si channels. However, the Sn solubility is, in equilibrium, limited to maximum 1%.

Using molecular beam epitaxy, imec demonstrated the epitaxial growth of high-quality GeSn with up to 8% substitutional Sn. Also, GeSn (with 2-8% Sn) materials that have been proved to be compatible with source/drain engineering processes (B implantation and activation and NiGeSn formation).

A low thermal budget has been determined for those processes on GeSn alloys. Temperatures must be lower than 600°C for B activation and lower than 450°C for NiGeSn formation.

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