Researchers develop energy-efficient probabilistic computer
Researchers from Tohoku University and the University of California, Santa Barbara have developed a probabilistic computer prototype that combines a complementary metal-oxide semiconductor (CMOS) circuit with a limited number of stochastic magnets, creating a heterogeneous probabilistic computer.
Developing computers capable of efficiently executing probabilistic algorithms frequently used in artificial intelligence and machine learning is a challenge that researchers are seeking to overcome. The approach outlined by researchers in this work represents a feasible solution, with the researchers confirming that the prototype’s enhanced computational performance and energy efficiency surpasses current CMOS technology. The research findings have been published in the journal Nature Communications.
Recent artificial intelligence and machine learning have had a transformational impact on society; in such technologies, probabilistic algorithms are utilised to solve problems where uncertainty is inherent or where an exact solution is computationally infeasible. These operations follow specific instructions within CMOS circuits, but sometimes inconsistencies can exist between how software (instructions) and hardware (circuits) work together, leading to discrepancies in outcomes. As the role of artificial intelligence and machine learning expands, there is rising demand for a new computing paradigm that can achieve greater sophistication while reducing energy consumption.
In this study, Professor Shunsuke Fukami from Tohoku University developed a near-future heterogeneous version of a probabilistic computer tailored for executing probabilistic algorithms and facile manufacturing. “Our constructed prototype demonstrated that excellent computational performance can be achieved by driving pseudo random number generators in a deterministic CMOS circuit with physical random numbers generated by a limited number of stochastic nanomagnets. Specifically speaking, a limited number of probabilistic bits (p-bits) with a stochastic magnetic tunnel junction (s-MTJ) should be manufacturable with a near-future integration technology,” Fukami said.
The researchers clarified that the final form of the spintronics probabilistic computer, primarily composed of s-MTJs, will yield a four-order-of-magnitude reduction in this area and a three-order-of-magnitude reduction in energy consumption compared to current CMOS circuits when running probabilistic algorithms.
Ultimately, the researchers’ prototype addresses the limitations of current deterministic CMOS circuits for artificial intelligence and machine learning. “We anticipate future research and development will advance, leading to the implementation in society of an innovative computing hardware that boasts exceptional computational performance and energy-saving capabilities,” Fukami said.
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