Basics of MOSFETs Part 2

The reach-through phenomenon occurs when the depletion region on the drift side of the body-drift p-n junction reaches the epilayer-substrate interface before avalanching takes place in the epi. Once the depletion edge enters the high carrier concentration substrate, a further increase in drain voltage will cause the electric field to quickly reach the critical value of 2 x 105 V/cm where avalanching begins.

The on-state resistance of a power MOSFET is made up of several components as shown in Figure 8:

R_DS(on) = R_source + R_ch + R_A + R_J + R_D + R_sub + R_wcml where:

R_source = source diffusion resistance;

R_ch = channel resistance;

R_A = accumulation resistance;

R_J = 'JFET' component-resistance of the region between the two body regions;

R_D = drift region resistance;

R_sub = substrate resistance.

Figure 8: Origin of internal resistance in a power MOSFET.

Wafers with substrate resistivities of up to 20 milliohm-cm are used for high-voltage devices and less than 5 milliohm-cm for low voltage devices.

R_wcml = sum of bond wire resistance, the contact resistance between the source and drain metallisation and the silicon, metallisation and leadframe contributions.

These are normally negligible in high-voltage devices but can become significant in low voltage devices.

Figure 9 shows the relative importance of each of the components to R_DS(on) over the voltage spectrum. As can be seen, at high voltages the R_DS(on) is dominated by epi resistance and the JFET component.

Figure 9: Relative contributions to R_DS(on) with different voltage ratings.

This component is higher in high-voltage devices due to the higher resistivity or lower background carrier concentration in the epi.

At lower voltages, the R_DS(on) is dominated by the channel resistance and the contributions from the metal to semiconductor contact, metallisation, bond wires and leadframe. The substrate contribution becomes more significant for lower breakdown voltage devices.

Transconductance, gfs, is a measure of the sensitivity of drain current to changes in gate-source bias. This parameter is normally quoted for a V_gs that gives a drain current equal to about half the maximum current rating value and for a VDS that ensures operation in the constant current region.

Transconductance is influenced by gate width, which increases in proportion to the active area as cell density increases. Cell density has increased over the years from around half a million per square inch in 1980 to around eight million for planar MOSFETs and around 12 million for the trench technology.

The limiting factor for even higher cell densities is the photolilthography process control and resolution that allows contacts to be made to the source metallisation in the centre of the cells.

Channel length also affects transconductance. Reduced channel length is beneficial to both gfs and on-resistance, with punch-through as a tradeoff.

The lower limit of this length is set by the ability to control the double-diffusion process and is around 1-2 mm today. Finally, the lower the gate oxide thickness the higher the gfs.

Threshold voltage, V_th, is defined as the minimum gate electrode bias required to strongly invert the surface under the poly and form a conducting channel between the source and the drain regions.

V_th is usually measured at a drain-source current of 250 µA. Common values are 2-4 V for high-voltage devices with thicker gate oxides, and 1-2 V for lower voltage, logic-compatible devices with thinner gate oxides.

With power MOSFETs finding increasing use in portable electronics and wireless communications where battery power is at a premium, the trend is toward lower values of R_DS(on) and V_th.

The diode forward voltage, VF, is the guaranteed maximum forward drop of the body-drain diode at a specified value of source current.

Figure 10 shows a typical I-V characteristic for this diode at two temperatures. P-channel devices have a higher VF due to the higher contact resistance between metal and p-silicon compared with n-type silicon.

Figure 10: Typical source-drain (body) diode forward voltage characteristics.

Maximum values of 1.6 V for high-voltage devices (greater than 100 V) and 1.0 V for low voltage devices (less than 100) are common.

The maximum allowable power dissipation that will raise the die temperature to the maximum allowable when the case temperature is held at 25°C is important. It is given by Pd where.

T_jmax = maximum allowable temperature of the p-n junction in the device (normally 150°C or 175°C) R_thJC = junction-to-case thermal impedance of the device.

When the MOSFET is used as a switch, its basic function is to control the drain current by the gate voltage. Figure 11(a) shows the transfer characteristics and Figure 11(b) is an equivalent circuit model often used for the analysis of MOSFET switching performance.

Figure 11: Power MOSFET (a) transfer characteristics, (b) equivalent circuit showing components that have greatest effect on switching.

The switching performance of a device is determined by the time required to establish voltage changes across capacitances. R_G is the distributed resistance of the gate and is roughly inversely proportional to active area.

L_s and L_D are source and drain lead inductances and are around a few tens of nH. Typical values of input (C_iss), output (C_oss) and reverse transfer (C_rss) capacitances given in the data sheets are used by circuit designers as a starting point in determining circuit component values.

Gate-to-drain capacitance, C_GD, is a nonlinear function of voltage and is the most important parameter because it provides a feedback loop between the output and the input of the circuit. It is also called the Miller capacitance because it causes the total dynamic input capacitance to become greater than the sum of the static capacitances.

Figure 12 shows a typical switching time test circuit. Also shown are the components of the rise and fall times with reference to the V_gs and VDS waveforms.

Figure 12: Switching time test (a) circuit, (b) V_gs and VDS waveforms.

Turn-on delay, t_d(on), is the time taken to charge the input capacitance of the device before drain current conduction can start. Similarly, turn-off delay, t_d(off), is the time taken to discharge the capacitance after the device is switched off. Although input capacitance values are useful, they do not provide accurate results when comparing the switching performances of two devices from different manufacturers.

Effects of device size and transconductance make such comparisons more difficult. A more useful parameter from the circuit design point of view is the gate charge rather than capacitance.

Most manufacturers include both parameters on their data sheets. Figure 13 shows a typical gate charge waveform and the test circuit. When the gate is connected to the supply voltage, V_gs starts to increase until it reaches V_th, at which point the drain current starts to flow and the CGS starts to charge. During the period t₁ to t₂, C_GS continues to charge, the gate voltage continues to rise and drain current rises proportionally.

Figure 13: Gate charge test (a) circuit, (b) resulting gate and drain waveforms.

At time t₂, C_GS is completely charged and the drain current reaches the pre-determined current I_D and stays constant while the drain voltage starts to fall. With reference to the equivalent circuit model of the MOSFET shown in Figure 13, it can be seen that with C_GS fully charged at t₂, V_gs becomes constant and the drive current starts to charge the Miller capacitance, CDG. This continues until time t₃.

Charge time for the Miller capacitance is larger than that for the gate to source capacitance C_GS due to the rapidly changing drain voltage between t₂ and t₃ (current = C dv/dt).

Once both of the capacitances C_GS and C_GD are fully charged, gate voltage (V_gs) starts increasing again until it reaches the supply voltage at time t₄.

The gate charge (Q_GS + Q_GD) corresponding to time t₃ is the bare minimum charge required to switch the device on. Good circuit design practice dictates the use of a higher gate voltage than the bare minimum required for switching and therefore the gate charge used in the calculations is Q_G corresponding to t₄.

The advantage of using gate charge is that the designer can easily calculate the amount of current required from the drive circuit to switch the device on in a desired length of time because Q = CV and I = C dv/dt, the Q = time x current.

For example, a device with a gate charge of 20 nC can be turned on in 20 µsec if 1 mA is supplied to the gate or it can turn on in 20 nsec if the gate current is increased to 1 A.

These simple calculations would not have been possible with input capacitance values. Peak diode recovery is defined as the maximum rate of rise of drain-source voltage allowed, ie, dv/dt capability.

If this rate is exceeded then the voltage across the gate-source terminals may become higher than the threshold voltage of the device, forcing the device into current conduction mode, and under certain conditions a catastrophic failure may occur.

There are two possible mechanisms by which a dv/dt induced turn-on may take place.

Figure 14 shows the equivalent circuit model of a power MOSFET, including the parasitic BJT.

Figure 14: Equivalent circuit of power MOSFET showing two possible mechanisms for dv/dt induced turn-on.

The first mechanism of dv/dt induced turn-on becomes active through the feedback action of the gate-drain capacitance, C_GD.

When a voltage ramp appears across the drain and source terminal of the device a current I₁ flows through the gate resistance, R_G by means of the gate-drain capacitance, C_GD. R_G is the total gate resistance in the circuit and the voltage drop across it is given by.

When the gate voltage V_gs exceeds the threshold voltage of the device V_th, the device is forced into conduction. The dv/dt capability for this mechanism is thus set by.

It is clear that low V_th devices are more probe to dv/dt turn-on. The negative temperature coefficient of V_th is of special importance in applications where high temperatures are present.

Also, gate circuit impedance has to be chosen carefully to avoid this effect.

The second mechanism for the dv/dt turn-on in MOSFETs is through the parasitic BJT as shown in Figure 15.

Figure 15: Physical origin of the parasitic BJT components that may cause dv/dt induced turn-on.

The capacitance associated with the depletion region of the body diode extending into the drift region is denoted as C_DB and appears between the base of the BJT and the drain of the MOSFET.

This capacitance gives rise to a current I₂ to flow through the base resistance R_B when a voltage ramp appears across the drain-source terminals. With analogy to the first mechanism, the dv/dt capability of this mechanism is.

If the voltage that develops across R_B is greater than about 0.7, then the base-emitter junction is forward-biased and the parasitic BJT is turned on.

Under the conditions of high (dv/dt) and large values of R_B, the breakdown voltage of the MOSFET will be limited to that of the open-base breakdown voltage of the BJT.

If the applied drain voltage is greater than the open-base breakdown voltage, then the MOSFET will enter avalanche and may be destroyed if the current is not limited externally.

Increasing (dv/dt) capability therefore requires reducing the base resistance R_B by increasing the body region doping and reducing the distance current ₂ has to flow laterally before it is collected by the source metallisation.

As in the first mode, the BJT-related dv/dt capability becomes worse at higher temperatures because R_B increases and V_BE decreases with increasing temperature.